Forksheet Metal Gate Layout With Trench Cut for Sub-10 nm Control
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is exacerbated by the constraints on lithographic processes used to pattern features, leading to trade-offs between critical dimension and spacing.
Innovation Solution
The implementation of a metal gate process with trench contact cuts, where a unified dielectric cut plug is used to form a pixel structure, followed by selective reconnection of cut gate and contact portions, and the use of a 'plug-last' approach to facilitate seamless work function metal deposition and reduce space constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down below 10 nanometer node, then increased density of functional units is achieved, but maintaining mobility improvement and short channel control becomes difficult
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional multi-gate structures (tri-gate, gate-all-around). By adding vertical dimensions and wrapping gates around channels, the invention achieves better electrostatic control and short channel effect suppression at scaled dimensions while maintaining high device density.
2Productivity
If multi-gate and nanowire transistors are scaled down, then increased number of devices per region is achieved, but constraints on lithographic processes become overwhelming
Solution Approach 1:
The patent segments the gate structure into multiple parts (multi-gate, nanowire segments) and uses self-aligned fabrication processes where previous structures serve as alignment references for subsequent steps. This segmentation with self-alignment reduces lithographic constraint complexity while enabling high device density.
3Area of stationary object
If uniform grid metal gate and trench contact cut is implemented, then space constraints are alleviated and metal fill capability is improved, but process complexity increases
Solution Approach 1:
The patent merges the gate cut and trench contact cut into a single unified process step using the same pixel structure definition. By combining these two previously separate patterning operations into one simultaneous process, the invention reduces overall process complexity while achieving the desired uniform grid layout and space utilization.
Data Source
AI summary
Integrated circuit structures having uniform grid metal gate and trench contact cut in a forksheet transistor architecture are described. In an example, a structure includes a dielectric backbone. First and second vertical stacks of nanowires are laterally adjacent to and in contact with first and second sides, respectively, of the dielectric backbone. First and second gate electrodes are around the first and second vertical stacks of nanowires, respectively, and are in contact with the first and second sides of the dielectric backbone, respectively. A first dielectric cut plug structure is adjacent to and in contact with the first gate electrode. A second dielectric cut plug structure is adjacent to and in contact with the second gate electrode. The second dielectric cut plug structure is parallel with the first dielectric cut plug structure.