Forksheet Transistor Isolation Wall Layout for Dense 3D Stacking
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving higher device density and performance while minimizing miniaturization and reducing short-circuit risks in forksheet transistor structures.
Innovation Solution
A 3D-stacked semiconductor device with forksheet transistors is designed, featuring an isolation wall that electrically isolates parallel nanosheet transistors and includes active contacts that contact the isolation wall, reducing short-circuit risks and enabling additional area gain through optimized manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If nanosheet transistors are vertically stacked to increase device density, then device density and current control are improved, but short-circuit risks between adjacent transistors increase
Solution Approach 1:
The patent introduces isolation walls that physically divide and segment the channel structures of vertically stacked nanosheet transistors. These isolation walls create distinct separated regions, preventing electrical short-circuits between adjacent transistors while maintaining high vertical integration density. The segmentation allows each transistor to operate independently without interference from neighboring devices.
Solution Approach 2:
The isolation wall acts as an intermediary structure between adjacent nanosheet transistors. This intermediate element provides electrical isolation and prevents direct contact between channel structures of different transistors, thereby eliminating short-circuit paths while allowing the transistors to remain in close proximity for high density.
2Volume of moving object
If forksheet transistor structure is implemented to achieve miniaturization, then device size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions where mandrel structures and sacrificial layers are formed before the final channel structures. This preliminary action simplifies the subsequent formation of complex forksheet geometries by using self-aligned processes, reducing the number of lithography steps and alignment requirements.
Solution Approach 2:
The forksheet transistor structure utilizes nested geometries where channel structures are formed within confined spaces defined by isolation walls and gate structures. This nesting approach allows complex 3D fork-shaped channels to be created through sequential deposition and etching steps, managing manufacturing complexity by building the structure layer by layer.
3Reliability
If isolation wall is introduced to prevent short-circuits, then electrical isolation is improved, but device area increases
Solution Approach 1:
The isolation walls are implemented as thin film structures that provide effective electrical isolation with minimal thickness. These thin film isolation walls create sufficient electrical barrier between adjacent transistors while occupying minimal lateral space, thus preventing short-circuits without significantly increasing the device footprint.
Data Source
AI summary
Provided is a semiconductor device which includes: a 1st source/drain pattern; a 2nd source/drain pattern; an isolation wall between the 1st source/drain pattern and the 2nd source/drain pattern; a 1st active contact on the 1st source/drain pattern; and a 2nd active contact on the 2nd source/drain pattern, wherein the 1st active contact contacts a 1st side surface of the isolation wall, and the 2nd active contact contacts a 2nd side surface of the isolation wall, opposite to the 1st sidewall.