Forksheet Transistor Structures for Nanosheet Channel Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to improve processing and manufacturing of integrated circuits (ICs) with smaller device sizes, particularly in transistors using nanowire channels, to enhance device density, carrier mobility, and drive current while addressing the limitations of existing fabrication methods.
Innovation Solution
The development of gate all-around (GAA) transistors, specifically forksheet transistors, where nanosheet channels are wrapped around by a gate electrode, with portions of a high-k dielectric layer laterally recessed to enhance control, using multi-patterning processes for precise feature formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is reduced to increase production efficiency, then productivity is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The fabrication process is divided into multiple sequential patterning steps (self-aligned double patterning) to achieve the desired nanoscale features. Each step forms a portion of the final pattern, allowing precise control at each stage rather than attempting to form all features in a single step, thus resolving the contradiction between miniaturization and manufacturing precision.
Solution Approach 2:
The patent utilizes vertical dimension (forming fins and nanosheet channels extending in the vertical direction) in addition to horizontal patterning. This three-dimensional approach allows for increased device density and better gate control while maintaining manufacturing precision through controlled epitaxial growth and selective etching processes.
2Quantity of substance
If transistor structure is changed to nanowire channels to increase device density, then device density is improved, but carrier mobility and drive current are reduced
Solution Approach 1:
The gate electrode completely surrounds the nanosheet channel in a curved/wrapped configuration rather than a planar arrangement. This gate-all-around structure provides superior electrostatic control over the channel, maintaining carrier mobility and drive current while achieving high device density through the vertical fin structure.
Solution Approach 2:
The patent employs composite material structures including alternating semiconductor layers (e.g., Si and SiGe) to form the nanosheet channels, with carefully selected material combinations to optimize both carrier mobility and device density. The high-k dielectric layers are also integrated to maintain electrical performance.
3Reliability
If gate electrode completely surrounds nanosheet channel for better control, then control over channel is improved, but device complexity increases
Solution Approach 1:
The gate electrode formation is performed as a preliminary step before final device completion. The gate structure is pre-formed with appropriate spacing and alignment, and subsequent processing steps (such as source/drain formation) are then performed. This sequencing simplifies the overall process by establishing control structures early when alignment is easier.
Solution Approach 2:
Self-aligned patterning techniques are used where the gate electrode structure serves as its own alignment reference for subsequent feature formation. The self-aligned double patterning process allows the gate structure to define the positions of source/drain regions and other features, reducing the need for additional alignment steps and simplifying manufacturing.
Data Source
AI summary
A semiconductor device structure includes a dielectric feature, the dielectric feature comprises a second dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, and a first dielectric layer in contact with exposed surfaces of the first sidewall and the second sidewall, a first semiconductor layer extending radially and in contact with the first dielectric layer on the first sidewall, and a first portion of a gate electrode layer surrounding at least three surfaces of the first semiconductor layer, wherein the first portion of the gate electrode layer has a surface separating from the first sidewall by a first distance, and an interface between the first dielectric layer and the first semiconductor layer is separated from the first sidewall by a second distance greater than the first distance.