Forksheet Nanosheet Transistor Structure for Higher Density Scaling
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to increase device density and improve processing efficiency while maintaining performance in transistors with reduced geometry sizes, particularly in nanowire channel devices.
Innovation Solution
The formation of a semiconductor device structure with nanosheet channels and forksheet transistors is achieved through a method involving the deposition of alternating semiconductor layers with different etch selectivity, followed by etching and deposition of dielectric and insulating materials to create fin structures, which are then processed to form forksheet transistors with enhanced density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is reduced to increase functional density, then production efficiency and cost are improved, but manufacturing precision and processing difficulty worsen
Solution Approach 1:
The transistor channel is segmented into multiple nanosheets (first semiconductor layers) stacked vertically, with each nanosheet forming a separate conduction path. This segmentation allows the device to achieve higher functional density without reducing the overall device footprint, thereby maintaining manufacturing precision while improving productivity
Solution Approach 2:
The invention transitions from planar transistor architecture to a vertical stacking architecture where multiple nanosheet channels are arranged in the vertical dimension. This dimensional change enables increased device density without compromising the lateral manufacturing precision, as each nanosheet maintains its individual integrity during fabrication
2Productivity
If nanowire channel transistors are used to increase device density, then functional density is improved, but device complexity and processing difficulty increase
Solution Approach 1:
Multiple nanosheet channels are merged into a single unified transistor structure sharing common source and drain regions. This merging approach increases device density while reducing the number of separate processing steps compared to implementing multiple discrete nanowire transistors, thereby lowering overall device complexity
Solution Approach 2:
The stacked nanosheet structure serves multiple functions simultaneously: each nanosheet acts as an independent conduction channel while collectively forming a high-density transistor array. The gate electrode structure also provides all-around control for multiple channels, achieving multi-functionality without proportionally increasing device complexity
3Productivity
If alternating semiconductor layers with different etch selectivity are deposited, then nanosheet channel formation is enabled, but manufacturing process complexity increases
Solution Approach 1:
Sacrificial layers (second semiconductor layers) are introduced as intermediary structures during fabrication. These sacrificial layers enable the formation of suspended nanosheet channels through selective etching, while their temporary presence simplifies the overall manufacturing process by providing a self-aligned framework for nanosheet positioning and gate electrode formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher device density and superior area and performance scalability, suitable for high-speed and low-power applications, by utilizing nanosheet channels surrounded by a gate electrode, with improved processing efficiency.
Implementation Method 1
The formation of a semiconductor device structure with nanosheet channels and forksheet transistors is achieved through a method involving the deposition of alternating semiconductor layers with different etch selectivity
Data Source
AI summary
A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.