Forksheet Nanosheet Transistor Layout for Tighter Fin Spacing
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing smaller and more complex integrated circuits due to the need for improved processing and manufacturing techniques as device size reduces, particularly in achieving greater device density and carrier mobility with transistors using nanowire channels.
Innovation Solution
The method involves forming a stack of semiconductor layers with alternating materials for nanosheet channels, using a sacrificial layer and dielectric features to create fin structures and gate electrodes, and employing multi-patterning processes to achieve tighter fin-to-fin spacing and fork-like nanosheet transistors for increased device density and performance scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced to increase functional density, then the number of interconnected devices per chip area increases, but manufacturing precision and processing difficulty worsen
Solution Approach 1:
The transistor channel is segmented into multiple nanosheet channels (first nanosheet channel and second nanosheet channel) formed from alternating semiconductor layers. This segmentation allows for increased functional density while maintaining manufacturable dimensions through self-aligned formation processes.
Solution Approach 2:
The patent employs a nested structure where gate electrodes surround the nanosheet channels in a gate-all-around configuration, and multiple nanosheet channels are nested within the same footprint area. This nesting approach increases functional density without proportionally increasing device area.
2Quantity of substance
If nanowire channels are used to achieve increased device density, then device density increases, but processing complexity increases
Solution Approach 1:
Sacrificial layers are formed between the alternating semiconductor layers before the nanosheet channels are fully defined. These sacrificial layers guide the self-aligned formation of the nanosheet channels and gate electrodes, simplifying the overall processing by pre-establishing the structural framework.
Solution Approach 2:
The patent transitions from planar transistor structures to three-dimensional gate-all-around nanosheet channels. This dimensional change allows for increased device density by utilizing vertical space and provides superior electrical control through the surrounding gate configuration.
3Quantity of substance
If device size is reduced to increase functional density, then the number of interconnected devices per chip area increases, but carrier mobility deteriorates
Solution Approach 1:
The patent uses alternating semiconductor layers with different materials properties (e.g., different bandgaps or crystal structures) to create local quality variations. This allows optimization of carrier mobility in specific regions while maintaining high device density through the multi-nanosheet structure.
Solution Approach 2:
The transistor channel consists of composite structures with alternating semiconductor layers, potentially including different material compositions (e.g., Si/SiGe or III-V/Si combinations). This composite approach enables tailored carrier mobility characteristics while achieving high functional density.
Data Source
AI summary
A method for forming a semiconductor device structure includes forming first, second, and third fin structures from a substrate, wherein the first fin structure includes a first plurality of semiconductor layers, the second fin structure includes a second plurality of semiconductor layers, and the third fin structure includes a third plurality of semiconductor layers, and wherein each of the first, second, and third plurality of semiconductor layers comprises first semiconductor layers and second semiconductor layers. The method includes forming an insulating material between the first, second, and third fin structures, forming an end cut in the second fin structure, the end cut exposing an upper portion of the substrate, forming a dielectric fin in the end cut, forming a first dielectric feature on the insulating material and between the first fin structure and the dielectric fin, forming a second dielectric feature on the insulating material and between the dielectric fin structure and the third fin structure, forming a sacrificial gate stack on a portion of the first fin structure, the second fin structure, the third fin structure, the first dielectric feature, and the second dielectric feature, removing a portion of the first fin structure, the third fin structure, and the dielectric fin not covered by the sacrificial gate stack, removing the sacrificial gate stack to expose portions of the first, second, and third fin structures, removing the second semiconductor layers of the first, second, and third plurality of semiconductor layers, and forming a gate electrode layer to surround at least three surfaces of the first semiconductor layers of the first, second, and third plurality of semiconductor layers.