Forksheet Nanosheet Gate Structure for Higher Device Density
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down device size while maintaining device performance and increasing device density, particularly in the manufacturing of nanosheet channel FETs, where achieving optimal geometry and manufacturing efficiency is crucial.
Innovation Solution
The method involves forming a stack of semiconductor layers with alternating materials of different etch selectivity and oxidation rates, using multi-patterning processes to create fin structures and dielectric features, and forming gate electrode layers around nanosheet channels to enhance device density and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced to increase device density, then functional density increases, but manufacturing precision and processing difficulty worsen
Solution Approach 1:
The channel region is segmented into multiple nanosheets stacked vertically, with each nanosheet forming a separate conducting path. This segmentation allows the device to achieve higher functional density by stacking multiple channels in the vertical dimension while maintaining manufacturable geometry for each individual nanosheet layer
Solution Approach 2:
The invention transitions from planar 2D channel structures to 3D vertically-stacked nanosheet channels. By utilizing the vertical dimension for stacking multiple nanosheets, the device achieves increased functional density without proportionally reducing the lateral geometry dimensions, thus maintaining manufacturing feasibility
2Reliability
If nanosheet channel geometry is optimized to increase carrier mobility, then device performance improves, but device complexity increases
Solution Approach 1:
Different material layers are used for different functional regions: semiconductor layers for high-mobility channel regions, sacrificial layers for structural definition, and dielectric layers for isolation. This local quality differentiation optimizes carrier mobility in the channel while managing overall device complexity through functional specialization
Solution Approach 2:
The device employs composite material stacks including alternating semiconductor and sacrificial layers, where each material is selected for its specific properties. The semiconductor layers provide high carrier mobility, while sacrificial layers enable precise nanosheet formation through selective etching, together achieving performance goals without excessive complexity
3Manufacturing precision
If multi-patterning processes are used to create fin structures, then manufacturing precision improves, but productivity decreases
Solution Approach 1:
Sacrificial layers are formed and patterned in advance before the actual nanosheet channel formation. This preliminary structuring enables subsequent self-aligned etching processes that achieve high precision fin and nanosheet geometries without requiring multiple complex patterning steps, thus maintaining productivity
Solution Approach 2:
Sacrificial layers serve as intermediary structures that define the nanosheet geometry during fabrication. These temporary structures enable precise pattern transfer through selective etching, achieving high manufacturing precision for the final channel structures while streamlining the overall fabrication process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased device density and improved performance scalability, enabling the production of smaller, more efficient semiconductor devices with reduced manufacturing costs.
Implementation Method 1
a stack of semiconductor layers including alternating first and second semiconductor layers are formed over a substrate, the first and second semiconductor layers having different etch selectivity
Implementation Method 2
the first and second semiconductor layers having different etch selectivity and oxidation rates
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.