Forksheet OTP Memory Cells Using PUF for Unclonable Security

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Solution Overview

Problem

Existing one-time programming (OTP) memory cells lack secure data protection and unique identity generation, as they cannot prevent data duplication and do not utilize manufacturing variations effectively for high-security applications.

Innovation Solution

The implementation of physically unclonable function (PUF) technology in OTP memory cells using forksheet transistors, where the memory cells are designed with specific nanowire and gate structures to generate a unique random code through quantum-tunneling, ensuring data security and unclonability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional OTP memory cells are used, then data storage is achieved, but data security and unique identity generation are lacking

Engineering Contradiction:
Improvedata securityVSAvoidunique identity generation capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent changes the physical parameters of the memory cell by introducing manufacturing variations (dimensional variations, material composition variations) that create unique electrical characteristics for each cell. These parameter variations enable the generation of unique random codes based on the natural differences in transistor threshold voltages and channel dimensions, thereby providing both data security and unique identity generation capability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces conventional mechanical/electrical switching mechanisms with quantum mechanical effects (quantum tunneling) in the antifuse structure. The quantum tunneling effect creates an irreversible breakdown that generates unique binary states, substituting traditional electrical programming mechanisms with quantum-level physical phenomena to achieve unclonable security features

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If manufacturing precision is increased, then device performance is improved, but manufacturing variations are reduced

Engineering Contradiction:
Improvedevice performanceVSAvoidrandom code uniqueness
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent converts the harmful effect of manufacturing variations (which typically degrade device performance) into a beneficial feature for security. By deliberately designing the memory cell to exploit these variations, the patent transforms unavoidable manufacturing imperfections into unique identifying characteristics that enable unclonable random code generation, thereby converting a disadvantage into a security advantage

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The PUF-based OTP memory cells provide secure data protection by generating a unique random code based on manufacturing variations, preventing data duplication and enhancing security in high-security applications.

Implementation Method 1

one of the first gate dielectric layer and the second gate dielectric layer in the first antifuse transistor is ruptured

Methodology Applied
Scientific EffectQuantum-tunneling:

Data Source

PatentUS20240395863A1One time programming memory including forksheet transistors and using physically unclonable function technology
Publication Date: 2024.11.28 EMEMORY TECH INC
  • US20240395863A1 patent drawing
  • US20240395863A1 patent drawing
  • US20240395863A1 patent drawing

AI summary

An OTP memory using a PUF technology includes a first memory cell. The first memory cell includes an antifuse transistor, a first select transistor and a second select transistor. The antifuse transistor includes a first nanowire, a second nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first portions of the first nanowire and the second nanowire are contacted with the isolation wall. The second portions of the first nanowire and the second nanowire are covered by the first gate structure. The first drain/source structure is electrically connected with the first terminals of the first nanowire and the second nanowire. The second drain/source structure is electrically connected with a second terminal of the second nanowire, but not electrically connected with a second terminal of the first nanowire.