Forksheet Buried Power Rail Isolation for Via Alignment
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Solution Overview
Problem
The alignment of buried power rails with vias in integrated circuit chips, particularly for forksheet devices, is challenging due to wafer deformation during bonding, leading to difficulties in powering separate transistor structures without electrical contact between them.
Innovation Solution
A method involving the formation of shallow trench isolations and a dielectric wall extension from the backside of the semiconductor substrate, allowing for the separation of buried power rails and enabling precise alignment and electrical insulation between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If buried power rails are used to power separate transistor structures in forksheet devices, then power delivery efficiency is improved, but alignment precision between power rails and vias deteriorates due to wafer deformation
Solution Approach 1:
The patent divides the substrate into multiple isolation regions using shallow trench isolation structures, which segment the continuous substrate into discrete areas. This segmentation allows independent positioning and alignment of buried power rails relative to specific device regions, compensating for wafer deformation effects by confining alignment requirements to smaller, more manageable zones rather than requiring global alignment across the entire wafer.
Solution Approach 2:
The patent introduces shallow trench isolation structures as intermediary elements between the buried power rails and the device regions. These isolation structures serve as reference features and physical barriers that facilitate precise alignment of power rails to vias while preventing electrical interference. The isolation regions act as mediators that decouple the alignment requirements from direct wafer deformation effects.
2Reliability
If shallow trench isolation and dielectric wall extension are formed from the backside, then electrical insulation between power rails is improved, but manufacturing complexity increases
Solution Approach 1:
The patent inverts the conventional manufacturing sequence by forming shallow trench isolation structures and dielectric wall extensions from the backside of the substrate rather than from the frontside. This inversion allows the isolation structures to be formed after the device regions are already in place, enabling precise alignment and electrical insulation without requiring complex frontside processing steps. The backside formation approach simplifies the overall manufacturing complexity while maintaining high reliability of electrical insulation.
Data Source
AI summary
Integrated circuit chips and method for making integrated circuit chips are provided. The method includes providing a semiconductor substrate, forming a device layer including a forksheet device on the substrate and providing the substrate with a substrate part of a dielectric wall of the forksheet device, a first shallow trench isolation and a second shallow trench isolation. The method also includes contacting a source or drain contact and extending into the substrate between the first shallow trench isolation and the dielectric wall, then removing the substrate material so as to expose an end of the dielectric wall, the first surface, and the second surface, then obtaining a first spacer and a second spacer, so as to obtain a trench, wherein the end of the dielectric wall is exposed to the trench, then depositing an electrically insulating material in the trench so as to form an extension.