Forksheet Semiconductor Structure With Self-Aligned Gate Isolation
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Solution Overview
Problem
The existing methods for fabricating Forksheet devices face challenges in achieving accurate gate isolation between nFET and pFET devices as feature sizes decrease, leading to inaccuracies and incomplete gate removal due to limitations in photolithography and etching techniques, affecting device performance.
Innovation Solution
A semiconductor structure and fabrication method involving composite layers with channel layers and insulating walls, where a first gate electrode is formed between adjacent channel layers, and a second isolation layer penetrates into the first isolation layer, allowing for self-aligned isolation without additional photolithography and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography and etching methods are used for gate isolation, then manufacturing process is simpler, but manufacturing precision deteriorates due to inaccurate alignment and incomplete gate removal
Solution Approach 1:
The patent applies preliminary action by forming the second isolation layer to penetrate into the first isolation layer before completing the gate formation process. This pre-positioned isolation structure enables self-aligned gate removal, ensuring precise gate isolation without relying on subsequent photolithography and etching steps that would compromise alignment accuracy.
Solution Approach 2:
The patent implements self-service through self-aligned isolation where the second isolation layer automatically positions itself relative to the gate structure during formation. This self-alignment mechanism eliminates the need for additional photolithography and etching processes, allowing the structure to define its own isolation boundaries with high precision.
2Length of moving object
If feature size decreases, then device scaling improves, but manufacturing precision deteriorates due to limitations in photolithography and etching techniques
Solution Approach 1:
The patent replaces the mechanical photolithography and etching system with a self-aligned isolation mechanism. By using the second isolation layer that penetrates into the first isolation layer, the method substitutes conventional mechanical patterning processes with a structure-based self-alignment approach, achieving high precision gate isolation at reduced feature sizes without the limitations of photolithography resolution.
3Manufacturing precision
If additional photolithography and etching processes are used for gate isolation, then manufacturing precision improves, but productivity deteriorates due to increased process steps
Solution Approach 1:
The patent merges the gate isolation function into the existing isolation layer structure by forming the second isolation layer that penetrates into the first isolation layer. This integration combines multiple functions (isolation and gate definition) into a unified self-aligned structure, eliminating the need for separate photolithography and etching process steps, thereby maintaining high precision while improving fabrication throughput.
Data Source
AI summary
A semiconductor structure includes a substrate, a first isolation layer in the substrate, composite layers over the substrate, and a second isolation layer between adjacent composite layers. Each composite layer includes channel layers, an insulating wall isolating two parts of each channel layer electrically, and a first gate electrode between adjacent channel layers. The second isolation layer penetrates into the first isolation layer.