Forksheet GAA Transistor Spacers for Stronger Electrostatic Control
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Solution Overview
Problem
Conventional fork sheet transistors suffer from reduced electrostatic control due to weaker electrostatic control of semiconductor material nanosheets near the dielectric pillar, leading to undesirable capacitance penalties and potential etching issues during fabrication.
Innovation Solution
Incorporation of vertical and horizontal inner spacer portions made of dielectric material between the dielectric pillar and semiconductor nanosheets, providing enhanced electrostatic control and preventing gate structures from directly contacting the source/drain region, thus avoiding capacitance penalties and etching issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dielectric pillar is introduced between PFET and NFET to achieve tighter spacing and reduced cell height, then device integration density is improved, but electrostatic control of semiconductor nanosheets near the dielectric pillar deteriorates
Solution Approach 1:
A gate structure is introduced as an intermediary element between the dielectric pillar and the semiconductor nanosheets. This gate structure acts as a mediator that provides electrostatic control to the nanosheets in the region near the dielectric pillar, compensating for the weakened control caused by the dielectric pillar's presence while maintaining tight n-to-p spacing
Solution Approach 2:
The gate structure is segmented into multiple portions, including a first gate portion and a second gate portion on opposite sides of the dielectric pillar. This segmentation allows independent optimization of electrostatic control in different regions, with each gate portion specifically controlling the nanosheets adjacent to it, thereby resolving the electrostatic control issue near the dielectric pillar
2Length of stationary object
If tighter n-to-p spacing is achieved through dielectric pillar isolation, then effective cell height is reduced, but electrostatic control and capacitance performance deteriorate
Solution Approach 1:
The gate structure serves as an intermediary that restores electrostatic control in the reduced cell height environment. By positioning the gate structure between the dielectric pillar and the nanosheets, it provides the necessary electrostatic control that would otherwise be lost due to the tighter spacing and reduced cell height
Solution Approach 2:
The solution moves from traditional planar gate control to a three-dimensional gate-all-around structure that wraps around the nanosheets. This dimensional change provides electrostatic control from multiple directions (top, bottom, and sides), compensating for the reduced vertical control distance in the tighter spacing configuration
Data Source
AI summary
A semiconductor device is provided which includes a pair of fork sheet transistors. Each fork sheet transistor includes a plurality of vertically stacked, spaced apart semiconductor material nanosheets and a gate all around (GAA) structure formed on the semiconductor material nanosheets. The semiconductor device also includes a dielectric pillar, composed of a first dielectric material and located between the pair of fork sheet transistors. The semiconductor device further includes: first inner spacer portions, composed of a second dielectric material, located between the dielectric pillar and inner edges of the semiconductor material nanosheets of each fork sheet transistor; and second inner spacer portions, composed of the second dielectric material, and located between each of the semiconductor material nanosheets, above the semiconductor material nanosheets and below the semiconductor material nanosheets.