Forksheet Dielectric Spine Layout for Denser Logic and Memory Cells
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Solution Overview
Problem
Integrated circuit design faces challenges in maximizing footprint utilization due to limitations in transistor structure arrangement, particularly in reducing the size of memory and logic cells, which hinders power, performance, and area (PPA) optimization.
Innovation Solution
Incorporating forksheet devices with the same dopant type on both sides of the dielectric spine, allowing for the integration of both forksheet and gate-all-around (GAA) transistors within the same cell, enabling flexible cell boundary placement and enhanced PPA performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional transistor structures are used in standard cells, then manufacturing and design are simpler, but footprint utilization is not maximized and PPA performance suffers
Solution Approach 1:
The transistor channel is segmented into multiple nanosheets stacked vertically, with a dielectric spine dividing the structure into forks. This segmentation allows the transistor to occupy less horizontal area while maintaining or increasing drive capability through multiple parallel conduction paths in the vertical dimension.
Solution Approach 2:
The invention transitions from planar 2D transistor structures to 3D vertical structures by stacking multiple nanosheets. This dimensional change enables better footprint utilization by exploiting the vertical space above the substrate, allowing more transistors to be packed into the same horizontal area.
2Area of stationary object
If cell size is reduced to increase density, then area efficiency improves, but transistor arrangement flexibility is constrained
Solution Approach 1:
By moving to vertical stacking, the design gains flexibility in arranging transistors within smaller footprints. The vertical dimension provides additional space for transistor components and interconnections, allowing complex arrangements to be achieved within reduced horizontal boundaries.
Solution Approach 2:
The forksheet transistor structure serves multiple functions: it provides high drive capability through multiple nanosheets, enables dense packing for small cell areas, and offers configurable arrangements by varying the number and configuration of nanosheets on each side of the dielectric spine.
3Object-generated harmful factors
If forksheet devices with same dopant type are used on both sides of dielectric spine, then parasitic capacitance is reduced, but device structure complexity increases
Solution Approach 1:
The dielectric spine creates local asymmetry in the transistor structure, with source/drain regions on opposite sides having the same dopant type. This local quality configuration reduces parasitic capacitance between adjacent transistors while maintaining the electrical characteristics needed for device operation.
Data Source
AI summary
Techniques are provided herein to form semiconductor devices having cells that include forksheet devices with source or drain regions of the same dopant type on both sides of the forksheet dielectric spine. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to logic and memory cells. The forksheet devices may include all p-type source or drain regions on both sides of the dielectric spine or all n-type source or drain regions on both sides of the dielectric spine. Using forksheet devices with the same dopant type allows for both forksheet transistors and gate-all-around (GAA) transistors to be included within the same cell. The cell boundaries may also be placed along the forksheet dielectric spines rather than along gate cuts, which provides greater flexibility when designing multi-height cells.