Forksheet Transistor Spine Layout for Dense Sub-10 nm Scaling
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits poses challenges in maintaining mobility improvement and short channel control, particularly below the 10 nanometer node, while also facing constraints in lithographic processes that affect feature dimension and spacing.
Innovation Solution
The development of forksheet transistors with a dielectric or conductive spine addresses these challenges by reducing the spacing between transistors to the width of the spine, enabling increased density and improved interconnection architectures, and using a Faraday shield to prevent electrical coupling issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-gate and nanowire transistors are scaled down to increase density, then the number of devices per chip area increases, but maintaining mobility improvement and short channel control becomes difficult
Solution Approach 1:
The patent transitions from planar transistor architectures to three-dimensional nanowire and multi-gate structures. The nanowire channel extends vertically from the substrate, allowing the gate to wrap around and control the channel from multiple sides (top, bottom, and sidewalls). This dimensional change enables effective short channel control and mobility improvement even as horizontal feature sizes scale down, resolving the contradiction between increased device density and maintained device performance.
Solution Approach 2:
The gate structure is nested around the nanowire channel in a concentric arrangement, with the gate wrapping completely around the channel. This nested configuration allows the gate to exert control from all directions, providing superior electrostatic control over the channel compared to planar gates. The multi-gate structure effectively surrounds the channel, enabling maintained performance at scaled dimensions.
2Quantity of substance
If transistor dimensions are reduced below 10 nanometer node, then device density increases, but maintaining performance becomes increasingly challenging
Solution Approach 1:
By moving to vertical nanowire channels and multi-gate structures, the patent achieves effective channel control without requiring proportional reduction in all dimensional tolerances. The vertical dimension provides an additional degree of freedom for controlling the channel, allowing performance to be maintained even as horizontal feature sizes approach and below 10 nanometers.
Solution Approach 2:
The patent employs composite material structures including semiconductor-sacrificial semiconductor layer pairs with different etch selectivities, enabling precise nanowire formation at scaled dimensions. The use of different materials with complementary properties (e.g., selective etching characteristics) allows for accurate definition of sub-10nm features that would be difficult to achieve with single-material systems.
3Manufacturing precision
If lithographic processes are pushed to pattern smaller features, then critical dimension decreases, but spacing between features becomes constrained
Solution Approach 1:
The patent resolves the lithographic spacing constraint by moving critical features into the vertical dimension. The nanowire channels extend vertically from the substrate, and multiple nanowires can be packed closely in the horizontal plane since their primary functional dimension is vertical. This allows small horizontal spacing between nanowire structures while maintaining adequate functional separation through vertical stacking and isolation.
Solution Approach 2:
The patent segments the channel into multiple discrete nanowires that can be independently formed and controlled. Each nanowire is a separate vertical structure that can be patterned using standard lithographic techniques, allowing flexible spacing arrangements. The segmentation into individual nanowires enables dense horizontal packing while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The forksheet transistor architecture achieves higher density and improved performance by stacking transistor strata and providing compact interconnect architectures, while the Faraday shield effectively screens electrical coupling, enhancing the reliability and efficiency of integrated circuit structures.
Implementation Method 1
using a Faraday shield to prevent electrical coupling issues
Data Source
AI summary
Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.