Forksheet Stacked FETs with Etch-Stop Middle Isolation

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional stacked transistors face issues with over-etching during the fabrication process, leading to damage of middle isolation regions and lower transistors, which affects the integrity and performance of the device.

Innovation Solution

The introduction of a forksheet stacked FET structure with a dielectric wall and integral middle isolation regions, including an etch-stop layer that protects lower transistors from over-etching by using the same insulating material as the dielectric wall and middle isolation regions, thereby maintaining the structural integrity and reducing damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional stacked transistor fabrication is used, then transistor density can be increased, but over-etching occurs causing damage to middle isolation regions and lower transistors

Engineering Contradiction:

Improvetransistor densityVSAvoidintegrity of middle isolation regions and lower transistors

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

An etch-stop layer is introduced as an intermediary component between the middle isolation region and the lower transistor. This etch-stop layer selectively prevents etching from penetrating into the lower transistor while allowing the upper transistor to be properly etched, thus protecting the lower transistor from over-etching damage

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The isolation structure is segmented into multiple functional regions: the middle isolation region for electrical isolation, and the etch-stop layer for process control. This segmentation allows each layer to perform its specific function independently, with the etch-stop layer preventing unwanted etching propagation

Inventive Principle:

Principle #1Segmentation

2Ease of manufacture

If conventional isolation structures are used, then fabrication can proceed, but rounding and damage occur to the middle isolation regions

Engineering Contradiction:

Improvefabrication processabilityVSAvoidprofile of middle isolation regions

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The etch-stop layer is positioned beforehand to cushion and stop the etching process before it can damage the middle isolation region. This preventive measure ensures that the middle isolation region maintains its sharp profile without rounding or damage during the upper transistor etching process

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentEP4601433A1Forksheet stacked transistor structure having middle isolation region, and related fabrication method

Publication Date: 2025.08.13 SAMSUNG ELECTRONICS CO LTD

Figure 1A
Figure 1b
Figure 2A~2B

AI summary

Forksheet stacked field-effect transistor (FET) devices are provided. A forksheet stacked FET device includes a first stacked FET (116a) having a first lower FET (LTa) and a first upper FET (UTa). The forksheet stacked FET device includes a second stacked FET (116b) that is adjacent the first stacked FET (116a). The second stacked FET (116b) has a second lower FET (LTb) and a second upper FET (UTb). The forksheet stacked FET device includes a dielectric wall (134) that is between the first lower FET (LTa) and the second lower FET (LTb). The forksheet stacked FET device includes a middle isolation region (136) having a first portion that is between the first lower FET (LTa) and the first upper FET (UTa), and a second portion that is between the second lower FET (LTb) and the second upper FET (UTb). Related methods of forming stacked FET devices are also provided.