Forksheet Transistor Structures Using Stacked Nanosheets for Higher Density
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to achieve increased device density and improved performance in transistors as device size reduces, particularly in nanowire channels, while maintaining efficient processing and manufacturing.
Innovation Solution
The formation of nanosheet transistors with forksheet structures is achieved by alternating semiconductor layers with different etch selectivity and oxidation rates, using multi-patterning processes to create fin structures and dielectric features, and forming gate electrodes that surround the channels, enabling higher device density and superior scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced to increase device density, then functional density increases, but manufacturing precision requirements worsen
Solution Approach 1:
The transistor channel is segmented into multiple nanosheets stacked vertically, with each nanosheet providing a separate conduction path. This segmentation allows the device to achieve higher effective channel width and density without proportionally reducing the lateral geometry dimensions, thereby maintaining manufacturing precision while increasing functional density
Solution Approach 2:
The invention transitions from planar 2D channel structures to three-dimensional stacked nanosheet channels. By utilizing the vertical dimension, multiple channels are stacked above each other, effectively increasing the channel width and device density without proportionally reducing the lateral footprint, thus maintaining manufacturability while achieving higher density
2Quantity of substance
If nanowire channels are used to achieve increased device density, then functional density improves, but processing complexity worsens
Solution Approach 1:
The gate electrode structure is designed to provide all-around coverage of the nanosheet channels, serving multiple functions simultaneously: electrical control of channel conduction, mechanical support for the stacked nanosheets, and definition of the device active region. This multi-functionality simplifies the overall processing by consolidating multiple structural requirements into a single integrated component
Solution Approach 2:
The nanosheet channels are nested within dielectric material, which is in turn surrounded by the gate electrode. This nested structure allows the channels to be embedded and protected while maintaining precise spatial relationships, simplifying the processing sequence by forming structures in concentric layers rather than requiring complex simultaneous patterning
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for greater device density and improved performance by creating forksheet transistors with enhanced channel width and reduced spacing, suitable for high-speed and low-power applications, while maintaining manufacturing efficiency.
Implementation Method 1
alternating semiconductor layers with different etch selectivity and oxidation rates
Implementation Method 2
alternating semiconductor layers with different etch selectivity and oxidation rates
Data Source
AI summary
A structure includes a first dielectric feature extending along a first direction, the first dielectric feature having a first side and a second side opposing the first side. The structure includes a first semiconductor layer disposed adjacent the first side of the first dielectric feature, the first semiconductor layer extending along a second direction perpendicular to the first direction. The structure includes a CESL in contact with the first dielectric feature and a portion of the first semiconductor layer, an ILD layer in contact with the CESL and a portion of the first semiconductor layer. The structure further includes a second dielectric feature extending along the first direction, the second dielectric feature including a first dielectric layer in contact with the CESL and a portion of the first semiconductor layer, and a second dielectric layer in contact with the first dielectric layer and a portion of the first semiconductor layer.