Forksheet Nanosheet Terminal-Cell Layout for Variation Control
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Solution Overview
Problem
The increase in off-current due to excessive scaling in gate length of transistors leads to significant power consumption issues in semiconductor integrated circuits, and there is a lack of examination on the structure of terminal cells using forksheet transistors in standard cell layouts.
Innovation Solution
A layout structure for semiconductor integrated circuits is proposed, incorporating terminal cells with forksheet transistors, where standard cells with and without logical functions are arranged in specific configurations to control variations in manufacturing and improve yield and reliability, utilizing nanosheets and gate interconnects to expose certain faces of nanosheets for reduced area and improved control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate length is scaled down to improve integration degree and operating speed, then transistor performance is improved, but off current increases significantly leading to higher power consumption
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional nanosheet FETs with fork-shaped gate electrodes. The nanosheet structure extends in the vertical dimension, providing multiple channel interfaces (top, bottom, and side surfaces) that enhance gate control over the channel. This dimensional change allows for better electrostatic control and reduced off-current while maintaining scaled dimensions, directly addressing the power consumption issue caused by excessive scaling.
2Reliability
If terminal cells are added to control manufacturing variations and improve yield, then reliability is improved, but layout complexity and area increase
Solution Approach 1:
The terminal cells incorporate the same nanosheet FET structure and fork-shaped gate electrode design as the functional standard cells. This universal design allows terminal cells to serve dual purposes: they provide manufacturing variation control at circuit boundaries while also maintaining design consistency and reusability across the entire standard cell library, reducing layout complexity through standardized components.
Solution Approach 2:
The patent uses dummy nanosheets and dummy gate interconnects in terminal cells that replicate the structure of functional cells without performing logical operations. This copying approach allows terminal cells to match the physical dimensions and manufacturing characteristics of functional cells, enabling effective variation control while maintaining layout regularity and simplifying the design process through reusable templates.
3Manufacturing precision
If fork-shaped gate electrodes are used in terminal cells, then manufacturing variation control is improved, but device structure complexity increases
Solution Approach 1:
The fork-shaped gate electrode features an asymmetric design with two prongs that extend on one side of the nanosheet while leaving the other side exposed. This asymmetric configuration is specifically tailored to control manufacturing variations at cell boundaries by providing enhanced gate control where needed, while the exposed nanosheet face maintains compatibility with standard interconnect formation processes, balancing precision improvement with structural simplicity.
Data Source
AI summary
A terminal cell includes: third and fourth nanosheets formed at the same positions as first and second nanosheets, respectively, in the Y direction; and first and second dummy gate interconnects surrounding the peripheries of the third and fourth nanosheets, respectively, in the Y direction. Faces of the first and third nanosheets on one side in the Y direction are exposed from a first gate interconnect and the first dummy gate interconnect, respectively. Faces of the second and fourth nanosheets on one side in the Y direction are exposed from a second gate interconnect and the second dummy gate interconnect, respectively.