Forksheet Transistor Structure With Nanosheet Channels for Higher Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in scaling down transistor sizes while maintaining device performance and density, particularly in achieving increased carrier mobility and drive current with nanowire channels, which requires improved processing and manufacturing techniques.
Innovation Solution
The method involves forming a stack of semiconductor layers with alternating materials for nanosheet channels, using multi-patterning processes like double-patterning or multi-patterning to create fin structures and dielectric walls, and forming gate electrode layers to surround the nanosheet channels, enabling the integration of both n-channel and p-channel FETs in the same device structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional scaling methods are used to reduce transistor size, then device density increases, but carrier mobility and drive current deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet channels that extend vertically from the substrate. This dimensional change allows the channel to provide better electrostatic control and higher carrier mobility while maintaining small footprint, thus improving device density without sacrificing carrier transport performance.
Solution Approach 2:
The patent employs composite material structures including alternating layers of semiconductor materials (e.g., Si/SiGe) to form the nanosheet channels. These composite structures enable selective etching processes and provide tailored electronic properties that enhance carrier mobility while maintaining structural integrity for high-density integration.
2Quantity of substance
If nanowire channels are used to increase device density and carrier mobility, then manufacturing complexity increases
Solution Approach 1:
The patent segments the channel structure into multiple thin nanosheet layers stacked vertically, which can be formed through sequential epitaxial growth. This segmentation approach allows better control over each individual layer's thickness and composition, simplifying the manufacturing process compared to forming monolithic nanowires while achieving higher device density.
Solution Approach 2:
The patent introduces sacrificial layers (e.g., SiGe layers) as intermediaries during the fabrication process. These sacrificial layers facilitate the formation of suspended nanosheet channels through selective release etching, enabling complex three-dimensional structures to be created using relatively simple planar processing techniques.
3Quantity of substance
If fin-to-fin spacing is reduced to increase device density, then manufacturing precision requirements increase
Solution Approach 1:
The patent moves the channel structure into the vertical dimension with nanosheets extending upward from the substrate. This allows device density to be increased through vertical stacking rather than horizontal compression, thereby reducing the stringent requirements for fin-to-fin spacing precision while maintaining high device density.
Data Source
AI summary
A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall. The structure also includes a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type. The structure further includes a gate bridge contact disposed on the first dielectric wall, and a gate via contact disposed on the gate bridge contact.