Formal Bug Hunting via Simulation-Guided Trace Generation
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Solution Overview
Problem
Formal verification in electronic circuit design is inefficient due to its exhaustive nature, which makes it unscalable for large designs, and often neglects complex paths, requiring manual intervention and uncontrolled trace generation.
Innovation Solution
A computer-implemented method for formal deep bug hunting that involves obtaining a start state for the device under test (DUT), selecting a subset of variables, generating a sequence of random values using a random number generator (RNG), and performing formal verification exploration, with features like dedicated seeds for RNGs and user-defined distribution decisions to control probability assignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification exhaustively checks all possible scenarios, then verification completeness is improved, but computational complexity and time required increase significantly
Solution Approach 1:
The patent segments the formal verification process into two distinct phases: (1) a simulation phase that generates representative traces using randomization and biasing techniques, and (2) a formal verification phase that uses these traces as starting points for targeted exploration. This segmentation allows the system to avoid exhaustively checking all possible scenarios while maintaining verification effectiveness by focusing on the most relevant state spaces identified during simulation.
Solution Approach 2:
The patent applies preliminary action by conducting simulation-based trace generation before formal verification. The simulation phase pre-explores the state space, generates representative traces, and identifies promising starting points. These preliminary results then guide the formal verification phase, which builds upon the simulation's insights rather than starting from scratch, thereby reducing the overall computational burden while maintaining thoroughness.
2Reliability
If formal verification uses exhaustive search, then verification thoroughness is improved, but scalability to large designs deteriorates
Solution Approach 1:
The patent introduces dynamics by making the verification approach adaptive rather than static. The system dynamically adjusts its behavior based on simulation results: it uses randomization and biasing during simulation to explore diverse state spaces, then leverages the generated traces to dynamically guide formal verification toward the most critical regions. This dynamic adaptation enables scalability to large designs by focusing computational resources on the most relevant areas identified through simulation.
Solution Approach 2:
The patent introduces simulation-generated traces as an intermediary between random simulation and formal verification. These traces serve as a bridge that captures essential behavioral patterns from simulation while providing structured starting points for formal verification. This intermediary mechanism enables the system to scale to large designs by translating the exploratory power of simulation into the rigor of formal verification without requiring exhaustive search.
3Ease of operation
If formal verification generates traces manually, then trace control and relevance are improved, but time consumption and labor requirements increase
Solution Approach 1:
The patent applies self-service by enabling the verification system to automatically generate and select its own traces without manual intervention. The simulation phase automatically generates traces using randomization and biasing, and the formal verification phase automatically uses these traces as starting points. This automation eliminates the need for manual trace crafting while maintaining high trace relevance through the systematic use of simulation-guided exploration.
4Measurement precision
If simulation uses random value generation with biasing, then scenario representativeness is improved, but control over generated values decreases
Solution Approach 1:
The patent introduces feedback by using the results of simulation (trace generation with biasing) to guide and constrain subsequent formal verification. The simulation phase generates representative traces using controlled randomization, and these traces then serve as feedback that shapes the formal verification exploration. This feedback mechanism allows the system to maintain scenario representativeness while regaining control through the structured use of simulation results to guide formal verification toward specific state spaces.
Data Source
AI summary
A method for formal deep bug hunting in a device under test (DUT) may include obtaining a selection of a start state for the DUT; obtaining a selection of one or a plurality of variables that are declared as random variables; for each of said one or a plurality of random variables, generating a sequence of random values in a generation order using a random number generator (RNG); and performing formal verification exploration of the DUT starting at the start state and consecutively assigning each of said one or a plurality of random variables a value from the sequence of values in the generation order.