Automated Formal Clock Domain Crossing Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional formal verification methods for clock domain crossings in electronic circuits are inadequate, lacking on-the-fly analysis and structural analysis capabilities, operating primarily at the block level, and requiring manual configuration, which is inconvenient and time-consuming, and often fail to verify clock domain crossings effectively due to memory consumption issues.
Innovation Solution
The implementation of automated formal clock domain crossing verification methods that identify and analyze clock domain crossing boundaries, extract relevant device components, synthesize and verify assertions, and perform iterative verification on a larger selection of the device, operating on the fly during the verification procedure, using bit-blasted approaches and formal verification techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional formal verification methods are used, then block-level verification can be performed, but comprehensive clock domain crossing verification is not achieved
Solution Approach 1:
The verification process is divided into multiple phases: pre-order traversal for identifier generation, in-order traversal for assertion generation, and post-order traversal for verification. This segmentation allows comprehensive clock domain crossing verification to be performed systematically without overwhelming complexity.
Solution Approach 2:
The patent introduces a temporal dimension to verification by generating assertions that check clock domain crossing conditions at different time points during signal propagation. This adds a new dimension to the verification space, enabling comprehensive coverage beyond traditional block-level verification.
2Productivity
If manual configuration is used, then verification can be performed, but the process is time-consuming and inconvenient
Solution Approach 1:
The verification system performs self-configuration by automatically generating verification assertions based on the circuit design. The system identifies clock domain crossing boundaries, generates appropriate assertions, and executes verification without requiring manual configuration, thereby improving both productivity and ease of operation.
Solution Approach 2:
The system performs preliminary analysis during the design phase to identify clock domain crossing boundaries and generate verification assertions in advance. This preliminary action eliminates the need for manual configuration during the verification phase, significantly reducing time consumption and improving productivity.
3Reliability
If comprehensive device analysis is performed, then thorough verification is achieved, but memory consumption increases
Solution Approach 1:
The verification process focuses on local clock domain crossing boundaries rather than analyzing the entire device uniformly. By identifying and verifying only the critical regions where clock domain crossings occur, the system achieves thorough verification of relevant areas while reducing overall memory consumption compared to comprehensive analysis.
Solution Approach 2:
The system performs partial verification by generating and checking only the necessary assertions for clock domain crossing boundaries. This selective approach verifies the critical aspects of clock domain crossings without requiring exhaustive analysis of all device components, thereby reducing memory requirements while maintaining verification reliability.
Data Source
AI summary
Methods and apparatus for performing automated formal clock domain crossing verification on a device are detailed. In various implementations of the invention, a device may be analyzed, wherein the clock domain crossing boundaries are identified. Subsequently, a formal clock domain crossing verification method may be applied to the identified clock domain crossing boundaries, resulting in clock domain crossing assertions being identified. After which the identified assertions may be promoted for post clock domain crossing analysis. With various implementations of the invention, a formal clock domain crossing method is provided, wherein the device components near an identified clock domain crossing are extracted. Assertions may then be synthesized and verified based upon the extracted components. Various implementations of the invention provide for clock domain crossing verification to be performed iteratively, wherein a larger and larger selection of the device is extracted during formal verification. Additionally, various implementations of the present invention provide that the clock domain crossing verification operate on the fly during a device verification procedure. With further implementations, a bit-blasted approach to clock domain crossing verification may be provided during formal verification.