Formal Verification of Deadlock in Multi-System SoC
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Solution Overview
Problem
Current formal verification methods for multi-system SoCs are inefficient in identifying and debugging complex interface and interconnect problems, requiring significant expertise and lacking the ability to leverage engineer expertise effectively, especially in verifying the absence of deadlock conditions.
Innovation Solution
A verification system that uses helper assertions derived from transaction definitions to analyze the RTL of multi-system SoCs, automatically extracting and optimizing assertions to prove the absence of deadlock conditions through formal analysis techniques like induction and theorem proving, aided by interactive tools to distinguish between intentional and unintentional transaction droppage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification methods are applied to multi-system SoCs, then the ability to verify deadlock conditions is improved, but the complexity of the verification process and expertise required increases significantly
Solution Approach 1:
The verification system segments the complex multi-system SoC into individual subsystems and interfaces, verifying each component separately before integrating results. This divides the overwhelming global verification problem into manageable local verification tasks, reducing the expertise burden while maintaining comprehensive coverage.
Solution Approach 2:
The patent introduces intermediary verification models and abstractions that mediate between the complex RTL design and the formal verification engine. These intermediaries simplify the verification process by providing standardized interfaces and reducing the direct complexity exposure to verification engineers.
2Difficulty of detecting and measuring
If comprehensive verification of all subsystem interfaces is performed, then the detection of interface and interconnect problems is improved, but the time and resources required increase significantly
Solution Approach 1:
The system performs preliminary verification by analyzing and verifying individual subsystems and interfaces before full system integration. This preliminary action identifies and resolves interface problems early in the design process, preventing compounding issues that would require more time to debug later.
Solution Approach 2:
The verification approach applies partial verification to critical interfaces and subsystems first, focusing verification resources on high-risk areas. This selective verification strategy provides sufficient confidence for complex interfaces without requiring exhaustive verification of every possible scenario, thereby reducing overall verification time.
3Productivity
If reusable semiconductor IP is integrated into SoCs, then design productivity is improved, but the complexity of verifying multi-system interactions increases
Solution Approach 1:
The verification system creates universal verification models and methodologies that can be applied across different reusable IP blocks and system configurations. This universal approach allows the same verification framework to handle diverse IP integrations, reducing the learning curve and expertise required for each new integration scenario.
Solution Approach 2:
The system employs self-verification capabilities where reusable IP blocks come with their own verification models and testbenches. This self-service approach allows IP blocks to verify their own interface correctness, reducing the burden on system-level verification while maintaining high productivity from IP reuse.
Data Source
AI summary
A verification system determines proof of the absence of a deadlock condition or other data-transport property in a multi-system SoC using helper assertions derived from a transaction definition. The verification system receives the circuit design information along with a transaction definition for one or more ports of the SoC. Once specified, the transaction definition is instantiated into the full system or subsystem RTL, generating an expanded RTL and a deadlock property. Data flow through the RTL is analyzed to extract helper assertions describing how the data flowed through the RTL. Helper assertions are automatically extracted to aid in the verification of the absence of a deadlock condition. Using the helper assertions, the formal engine applies one or more techniques to formally analyze the circuit design to prove the absence of a deadlock condition.