Formal Fault Propagation Analysis for Safety-Critical Systems
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Solution Overview
Problem
Current fault propagation analysis in safety-critical systems, such as automotive electronics, is inefficient due to the need for extensive simulation of various scenarios and manual identification of safe faults, which is labor-intensive, error-prone, and incomplete, especially when dealing with complex hardware safety mechanisms and millions of potential fault locations.
Innovation Solution
A computer-implemented method for sequential equivalency check that applies a more compact encoding of the equivalency problem, reduces circuit logic duplication, and leverages information about fault location and nature to efficiently model and diagnose faults, including transient faults, using formal checks and fault propagation analysis to identify non-propagatable faults and display fault propagation paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive simulation of various scenarios is performed to identify safe faults, then fault detection coverage is improved, but user effort and time consumption increase significantly
Solution Approach 1:
The patent segments the fault analysis process into two distinct phases: (1) a formal equivalence checking phase that efficiently identifies non-propagatable faults without extensive simulation, and (2) a targeted simulation phase that focuses only on propagatable faults. This segmentation resolves the contradiction by eliminating the need for exhaustive simulation of all faults while maintaining comprehensive fault detection coverage.
Solution Approach 2:
The patent performs preliminary formal equivalence checking to identify and eliminate non-propagatable faults before conducting simulation. This preliminary action filters out faults that cannot propagate to outputs, allowing subsequent simulation efforts to focus only on relevant propagatable faults, thereby significantly reducing overall simulation time and user effort while maintaining detection coverage.
2Measurement precision
If formal equivalence checking is applied to all faults, then identification accuracy is improved, but computational demands increase
Solution Approach 1:
The patent applies formal equivalence checking selectively rather than universally - specifically to identify non-propagatable faults at the outset. This partial application of formal methods provides high identification accuracy for the critical classification of non-propagatable versus propagatable faults, while avoiding the excessive computational burden of applying formal checking to every individual fault scenario throughout the entire analysis process.
3Device complexity
If circuit logic duplication is reduced for compact encoding, then device complexity is reduced, but equivalence checking accuracy may deteriorate
Solution Approach 1:
The patent extracts and removes redundant circuit logic duplication that does not contribute to fault propagation analysis. By identifying and eliminating unnecessary duplicated logic while preserving the essential circuit behavior needed for equivalence checking, the patent reduces device complexity without compromising the accuracy of fault identification.
Data Source
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AI summary
A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.