Formal Verification Coverage Metrics for Circuit Design Properties
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Solution Overview
Problem
The complexity of integrated circuit designs has increased, making formal verification a resource-intensive process that often results in incomplete analysis, where determining the extent of reachable state space is impractical, and existing tools lack effective metrics to assess verification coverage.
Innovation Solution
A computer-implemented method for generating formal verification coverage metrics by classifying cover items based on reachability analysis, providing coverage information that indicates the level of verification achieved within a specific bound, allowing designers to determine if further verification is needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is performed on complex circuit designs, then verification coverage is improved, but resource consumption (time and memory) increases significantly
Solution Approach 1:
The patent segments the verification process into two distinct phases: (1) a bounded reachability analysis phase that explores the state space up to a predetermined bound to identify reachable cover items, and (2) a formal verification phase that uses the identified reachable cover items as constraints. This segmentation allows the expensive formal verification to focus only on relevant portions of the state space, reducing overall resource consumption while maintaining verification coverage.
Solution Approach 2:
The patent performs preliminary reachability analysis before the main formal verification process. By pre-identifying reachable cover items and constructing constraints based on them, the system prepares the verification environment in advance, allowing the subsequent formal verification to proceed more efficiently with reduced resource requirements.
2Reliability
If formal analysis is performed to determine reachable state space, then verification completeness is improved, but computation hits resource limits
Solution Approach 1:
The patent applies partial action by performing reachability analysis only up to a predetermined bound rather than exploring the entire state space. This bounded exploration identifies a sufficient subset of reachable cover items needed for effective formal verification without requiring exhaustive analysis, thus avoiding resource limits while maintaining verification effectiveness.
3Measurement precision
If exhaustive simulation is performed to analyze all possible valid inputs, then verification accuracy is improved, but time consumption increases
Solution Approach 1:
The patent extracts and removes unreachable cover items from the verification process by using reachability analysis to identify and filter out state space regions that cannot be reached from the initial state. By eliminating these irrelevant portions beforehand, the formal verification focuses only on reachable and relevant cover items, achieving accurate verification without the time cost of exhaustive simulation of all possible inputs.
Data Source
AI summary
A computer-implemented method and non-transitory computer readable medium for circuit design verification. A property defined for a circuit design is received, the property having a cone of influence in the circuit design corresponding to a portion of the circuit design capable of affecting the property. Bounded reachability analysis is performed for the circuit design against a set of cover items. The set of cover items are classified into classified cover items based on results of the reachability analysis. Coverage information is generated indicating an amount of formal verification coverage provided by the property. The coverage information is generated based on a first set of the classified cover items that correspond to the cone of influence of the property and that are reached within a particular bound during the reachability analysis.