Formal Verification Coverage Metric Accuracy via Proof Core Extraction
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Solution Overview
Problem
Existing formal verification coverage metrics for circuit designs overestimate the coverage provided by property sets, leading to inadequate testing and potential economic impacts due to undetected design flaws.
Innovation Solution
A method that identifies a proof core within the cone of influence of a circuit design, which is sufficient to prove the correctness of a property, and generates a coverage metric based on this proof core, providing a more accurate representation of formal verification coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing formal verification coverage metrics are used to evaluate property sets, then verification process completes faster, but coverage accuracy deteriorates leading to overestimation of test coverage
Solution Approach 1:
The patent extracts and removes false positives from the coverage metric calculation by identifying and eliminating properties that incorrectly appear to be covered. This is achieved through a refined coverage metric that distinguishes between actual coverage and spurious coverage, thereby improving measurement precision without significantly impacting verification speed
Solution Approach 2:
The patent introduces an intermediary verification step that acts as a mediator between the property set and coverage metric calculation. This intermediary layer validates whether properties are truly covered before incrementing coverage metrics, preventing overestimation while maintaining efficient verification throughput
2Reliability
If property set is expanded to improve coverage, then test coverage increases, but verification time increases
Solution Approach 1:
The patent applies partial action by focusing verification efforts on the most critical properties and coverage areas. Rather than exhaustively verifying all possible properties, the system identifies and prioritizes high-impact properties that provide maximum coverage benefit, thereby improving reliability without proportionally increasing verification time
Solution Approach 2:
The patent implements feedback mechanisms where coverage metrics are continuously monitored and used to guide property selection and verification priorities. The system learns from previous verification results and adjusts the property set dynamically, ensuring that verification time is spent on properties that will most effectively improve coverage and reliability
Data Source
AI summary
The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and automatically identifying one or more code coverage points from a netlist of an original model associated with the electronic design. Embodiments may include receiving a property and one or more elements, each of the one or more elements corresponding to one of the one or more code coverage points. Embodiments may further include performing model checking based upon, at least in part, the property and the one or more elements. Embodiments may also include verifying the property and generating an unsatisfiability core based upon, at least in part, the one or more elements.