Formal Verification Engine for Multi-Clock Domain Electronic Circuit Design
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Solution Overview
Problem
In electronic design verification, especially in multi-clock domain designs, it is challenging to identify the root cause of contradictions in constraints, leading to inefficient formal verification processes due to the complexity of clock interactions and the need to test multiple clock configurations, which can result in bugs going unnoticed.
Innovation Solution
A computer-implemented method for formal verification that allows a formal engine to select and consider a range of clock factor values and phases, using a multiplexer with a ring counter to model all valid clock setups in a single formal model, ensuring all valid clock configurations are analyzed without manual interaction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate formal verification setups are used to test different clock configurations, then coverage of clock configurations can be improved, but device complexity and time consumption increase significantly
Solution Approach 1:
The patent merges multiple separate formal verification setups into a single unified verification environment. Instead of running multiple independent verification instances for different clock configurations, the system consolidates them into one setup that can handle multiple clock domains simultaneously. This is achieved by introducing a clock domain specification mechanism that defines relationships between different clock domains within a single verification context, thereby reducing overall system complexity while maintaining comprehensive coverage.
Solution Approach 2:
The verification system is designed with universal capabilities to handle multiple clock configurations through a single setup. The clock domain specification allows the system to universally accommodate different clock relationships (frequency ratios, phase differences, skew values) without requiring separate configurations. This multi-functional approach enables one verification environment to serve multiple testing purposes across various clock scenarios.
2Measurement precision
If fixed frequency ratio and phase difference are specified between clocks, then verification precision for specific configurations is improved, but adaptability to multiple clock configurations decreases
Solution Approach 1:
The system transitions from static, fixed clock relationship specifications to dynamic specifications that can adapt to multiple configurations. The clock domain specification introduces parameters such as frequency ratio ranges, phase difference ranges, and skew value ranges that can be dynamically adjusted. This allows the verification system to precisely verify specific clock relationships when needed while maintaining the flexibility to switch between different configurations without redefining the entire verification setup.
3Measurement precision
If manual analysis of constraint contradictions is performed, then root cause identification accuracy is improved, but time consumption and productivity decrease
Solution Approach 1:
The system implements automated feedback mechanisms that monitor constraint satisfaction across multiple clock domains during verification. When contradictions or violations occur, the system automatically traces back through the clock domain specifications and constraint relationships to identify the root cause. This feedback loop provides accurate diagnostic information about which clock relationship or constraint is causing verification failures, eliminating the need for manual analysis while maintaining high accuracy in root cause identification.
Data Source
AI summary
The present disclosure relates to a method for formal verification of an electronic design. Embodiments may include receiving, using a processor, an electronic design having a plurality of clock configurations associated therewith and identifying a target clock configuration associated with the electronic design. Embodiments may also include receiving a range of clock factor values from a user, wherein each clock factor value corresponds to a frequency of the target clock configuration. Embodiments may further include selecting, via a formal engine, at least one clock factor value from the range and selecting, via the formal engine, at least one clock phase associated with the target clock configuration. Embodiments may also include performing formal verification of the electronic design, based upon, at least in part, the at least one clock factor value or the at least one clock phase.