Formal Verification Environment Specification via GUI
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Solution Overview
Problem
Manual specification of design input behaviors for formal verification is labor-intensive and prone to errors, requiring careful balance to avoid false detection of design flaws or missing misbehaviors.
Innovation Solution
A graphical user interface-based method for assigning behaviors to design inputs, where design inputs are extracted from specifications, behavior options are read from a configuration file, and interactive assignment generates environment code for formal verification tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual specification of design input behaviors is performed using HDL or PSL, then verification accuracy is improved, but labor intensity and time consumption increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-defining environment templates with common design input behavior patterns before the actual verification task. These templates contain pre-configured HDL or PSL code for typical protocols and interfaces, allowing engineers to select and apply them directly without manual specification, thus reducing time consumption while maintaining verification accuracy through proven templates
Solution Approach 2:
The patent uses copying by creating reusable environment templates that can be replicated and applied to multiple design inputs. Once a correct environment specification is developed for one interface or protocol, it can be copied and adapted for similar cases, eliminating repetitive manual specification work while ensuring consistency and accuracy across multiple verification scenarios
2Reliability
If manual specification of design input behaviors is performed, then verification coverage is improved, but error probability increases
Solution Approach 1:
The patent implements feedback by providing automated validation that checks whether the selected environment template matches the actual design input characteristics. The system analyzes the design input, compares it with template requirements, and provides feedback on compatibility, allowing engineers to verify their selections and reducing errors from mismatched or incorrect environment specifications
Solution Approach 2:
The patent introduces an intermediary layer between the design input and the environment specification. This intermediary consists of automated analysis tools that examine the design input, identify required behaviors, and recommend appropriate templates. This intermediary reduces errors by acting as a check between the engineer's selection and the actual verification requirements
3Adaptability or versatility
If behavioral constructs are used in HDL for environment specification, then specification flexibility is improved, but tool compatibility deteriorates
Solution Approach 1:
The patent applies dynamics by making the environment specification approach adaptive rather than fixed. The system dynamically selects between using behavioral constructs or synthesizable constructs based on the specific verification tool being used and the requirements of the design input. This allows the specification method to flexibly adapt to different tool constraints while maintaining the ability to use sophisticated behavioral descriptions when appropriate
Data Source
AI summary
Computer-implemented techniques are disclosed for defining an environment for formal verification of a design-under-test. Initially there is extraction of design inputs by a design analysis module, and presentation of the inputs on a graphical user interface. Behavior options for the design inputs are offered on the graphical user interface for selection by an operator. Environment code that is descriptive of the design inputs and selected behavior options is emitted, typically in a hardware description language, for submission to a formal verification tool. A meta-code file containing the assigned behavior options is generated to aid subsequent sessions.