Formal Verification Equivalence Checking C++ to RTL
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Solution Overview
Problem
Conventional formal verification techniques are limited in synthesizing software specifications written using advanced language features, particularly in C++ or SystemC, which reduces their usability in evolving designs, and struggle with C/C++ versus register transfer level (RTL) sequential equivalence checking due to challenges in stimulating inputs and comparing outputs effectively.
Innovation Solution
A computer-implemented method that uses case split hints derived from abstract interpretation techniques to decompose the design state space into smaller partitions, performing abstraction operations to eliminate irrelevant design elements and model checking to determine accuracy, combining over-approximation and under-approximation techniques for automatic partitioning and refinement of abstract models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional formal verification techniques are used to check equivalence between C/C++ software specifications and RTL implementation models, then the verification process can be performed, but the techniques are limited in synthesizing software specifications with advanced language features and struggle with stimulating inputs and comparing outputs effectively
Solution Approach 1:
The patent applies segmentation by dividing the design state space into smaller partitions using case split hints. This decomposition allows the verification system to handle complex C/C++ specifications with advanced language features by breaking them into manageable segments, thereby improving both language coverage and verification reliability without being overwhelmed by the complexity of the entire design space
2Productivity
If the design state space is decomposed into smaller partitions using case split hints, then the equivalence checking becomes more manageable, but the complexity of generating and processing case split hints increases
Solution Approach 1:
The patent implements self-service by using abstract interpretation techniques to automatically generate case split hints from the software specification itself. The system extracts relevant information and partitioning strategies directly from the C/C++ code without requiring external guidance or manual intervention, thereby improving verification productivity while managing the complexity of proof decomposition through automated analysis
3Productivity
If abstraction operations are performed to eliminate irrelevant design elements, then the model checking becomes more efficient, but the accuracy of the abstract model may be reduced
Solution Approach 1:
The patent applies local quality by performing selective abstraction operations that eliminate only the specific design elements irrelevant to the particular property being verified. Rather than applying uniform abstraction across the entire model, the system tailors the abstraction to each verification context, maintaining high model accuracy where needed while improving efficiency by removing only necessary irrelevant details
Data Source
AI summary
The present disclosure relates to a computer-implemented method for use in a formal verification of an electronic design. Embodiments may include receiving a reference model including a software specification, an implementation model at a register transfer level, and a property that analyzes equivalence between the reference model and the implementation model. The method may further include generating one or more case split hints based upon the reference model, that may be used to decompose the design state space into smaller partitions and performing an abstraction operation on a portion of design logic associated with one or more partitions in order to eliminate design elements that are irrelevant to a particular property. Embodiments may also include performing model checking on the abstract models to determine their accuracy.