Formal Verification Structural Coverage via Fault Injection
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Solution Overview
Problem
Current formal verification methods lack a quantitative metric to determine structural coverage of register transfer level (RTL) designs, as they cannot ensure that all lines of a hardware description language (HDL) representation of an RTL design have been executed during operation, unlike simulation metrics which provide output coverage.
Innovation Solution
Introducing a control vector into the HDL code to modify segments and mimic faults, allowing for simulation and formal verification to detect these modifications, thereby determining which parts of the design are covered by the test suite and providing structural coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If formal verification methods are used to verify RTL designs, then mathematical proof of properties can be obtained, but quantitative structural coverage metrics cannot be provided
Solution Approach 1:
The patent creates a copy of the HDL design with injected faults (control vectors) that mimic manufacturing defects. By simulating the design with these injected faults and comparing outputs against expected values, the system generates quantitative structural coverage metrics that formal verification alone cannot provide. This copying approach allows measurement of which lines of HDL code execute under test conditions.
2Measurement precision
If simulation metrics are used to provide output coverage, then quantitative measurement is achieved, but structural coverage of HDL lines cannot be determined
Solution Approach 1:
The patent introduces control vectors that act as visible markers or 'colors' within the HDL code structure. These control vectors modify segments of the HDL code to create detectable differences when faults are injected. During simulation, the system checks whether these modified segments produce expected output changes, thereby making structural coverage measurable through the presence or absence of detected faults.
3Reliability
If all possible input conditions are tested to ensure completeness, then output coverage is achieved, but execution of all HDL lines cannot be guaranteed
Solution Approach 1:
The patent performs preliminary action by injecting faults into the HDL code before simulation. Control vectors are pre-placed throughout the design at strategic locations where faults would be detectable. This preliminary fault injection creates a framework where subsequent simulation can systematically exercise different HDL lines and determine which ones execute under given input conditions, thereby providing structural coverage information.
Data Source
AI summary
Some aspects of the present disclosure provide for a system and method to discover which parts of a design a formal test suite can detect faults in, and thus how much of a design structure is covered by a property set. A mutatable RTL design is defined which allows for modification of a part of an RTL design from its intended behavior to a non-intended behavior, thus introducing unwanted effects. The mutatable RTL design can then be synthesized to produce a functional representation of the design. The property set can be re-run on the synthesized design to see whether the functional representation of the design is sensitive to the unwanted effect and thus whether formal verification can detect the modification.