Formal Verification Model Generation via Intermediate Representation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional formal verification methods are limited in synthesizing software specifications written using advanced language features, leading to reduced usability in evolving designs, and the generated verification models are tightly integrated with implementation models, making standalone verification impossible.
Innovation Solution
A computer-implemented method that generates a formal verification model by receiving a specification model, creating an intermediate representation, applying semantic preserving program transformations, and synthesizing a semantically transformed model using machine-generated transformations and symbolic execution, allowing for equivalence checking and assertion-based verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional formal verification methods are used to synthesize software specifications, then verification can be performed, but language coverage is limited and usability is reduced in evolving designs
Solution Approach 1:
The patent introduces an intermediate representation (IR) as a mediator between the software specification and the formal verification model. This IR serves as a language-agnostic intermediate form that decouples the verification process from specific programming language features, thereby improving language coverage without proportionally increasing verification model complexity. The IR acts as a buffer that translates diverse language constructs into a unified formal representation.
2Reliability
If the verification model is tightly integrated with the implementation model for equivalence checking, then equivalence checking can be performed, but standalone verification becomes impossible
Solution Approach 1:
The patent segments the verification process into distinct components: the software specification, the intermediate representation, and the formal verification model. This segmentation allows the formal verification model to be generated independently from the implementation model, enabling standalone verification while maintaining verification accuracy. The intermediate representation serves as a bridge that preserves the necessary information for both equivalence checking and independent formal verification.
3Adaptability or versatility
If advanced language features are used in software specifications, then design functionality is enhanced, but synthesis capability is reduced
Solution Approach 1:
The intermediate representation serves as a mediator that translates advanced language features into a simplified, synthesis-friendly form. By introducing this intermediate layer, the system can accept software specifications with sophisticated language constructs while automatically transforming them into a representation that is easier to synthesize into formal verification models, thus resolving the contradiction between design capability and synthesis ease.
Data Source
AI summary
The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a specification model associated with an electronic design and generating, using a parser, an intermediate representation based upon, at least in part, the specification model. Embodiments may also include applying a machine generated semantic preserving program transformation to the intermediate representation to create a semantically transformed specification model and synthesizing the semantically transformed specification model to generate a formal verification model.