Formal Verification Invariants for Integrated Circuit Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional formal verification methods for integrated circuits are limited by their inability to efficiently handle large designs, as they can only process up to thousands of registers compared to millions handled in simulations, necessitating a more effective technique to leverage constraint solving for improved performance.
Innovation Solution
The method involves partitioning constraints based on variables, generating binary decision diagrams (BDDs), and deriving invariants such as constant, symmetric/implication, one-hot, and ternary invariants through cofactoring and minterm counting, which are then used to optimize formal verification processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional formal verification is used to ensure design correctness, then verification reliability is improved, but the scale of designs that can be handled is limited (thousands of registers vs. millions in simulation)
Solution Approach 1:
The patent segments the constraint set into multiple partitions based on variable overlap. Constraints are divided into groups where each partition contains constraints with non-overlapping variables, enabling independent processing and reducing memory requirements for large-scale designs
Solution Approach 2:
The patent transforms constraints into a different representation format using Binary Decision Diagrams (BDDs). This parameter change in representation enables more efficient storage and manipulation of constraint relationships, allowing verification of larger designs
2Reliability
If all transitions are considered in formal verification (implicit operation), then verification completeness is improved, but system resources and run-time increase significantly
Solution Approach 1:
The patent performs preliminary action by deriving invariants from the constraint BDDs before the actual verification process. These invariants (constant, symmetric/implication, one-hot, and ternary invariants) are pre-computed and then applied to filter invalid transitions, reducing the verification workload
Solution Approach 2:
The patent extracts invalid transitions from the verification process using derived invariants. By identifying and removing transitions that violate constraints before verification, the system reduces the number of transitions that need to be analyzed, decreasing run-time while maintaining completeness
3Measurement precision
If constraint sets are used to guide simulations with valid input values, then simulation accuracy is improved, but the complexity of constraint solving increases
Solution Approach 1:
The patent segments the constraint solving process by partitioning constraints into multiple groups based on variable overlap. This segmentation reduces the complexity of constraint solving by breaking down large constraint sets into smaller, more manageable partitions that can be processed independently
Solution Approach 2:
The patent introduces BDDs as an intermediary representation between constraints and verification. This intermediary structure simplifies constraint solving by providing an efficient data structure for representing and manipulating constraint relationships, reducing overall system complexity
Data Source
AI summary
A method of performing formal verification on a design for an integrated circuit can include accessing a set of constraints for the design. These constraints can be partitioned based on their variables, wherein any overlapping variables can result in the conjoining of their corresponding constraints. Binary decision diagrams (BDDs) can be generated based on such conjoining. Notably, invariants can be derived from the BDDs. These invariants can include constant, symmetric/implication, one-hot/zero-hot, and ternary invariants. Deriving the invariants can include cofactoring and counting of minterms of the BDDs. Using the invariants while performing formal verification on the design can advantageously optimize system performance.