Formal Verification of Deep Loop Circuits Using Microtransactions
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Solution Overview
Problem
Current formal verification methods for circuit designs, particularly those with deep loops, face challenges in scalability and efficiency due to high computational complexity and memory requirements, making it difficult to verify designs with numerous iterations, such as those with 100 or more loop iterations, as they often exceed the capacity of conventional tools and result in unacceptably long verification times.
Innovation Solution
The implementation of microtransaction-based verification techniques, which break down the verification process into sub-function-call-level transactions, allowing for loop flattening, selective stalling of RTL execution, delay insertion to align pipeline drain, and probe insertion to maintain state data, enabling verification at a finer transactional level and reducing computational overhead and memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional formal verification methods are used on designs with deep loops (100 or more iterations), then verification completeness is maintained, but verification time and computational complexity become unacceptably long and exceed tool capacity
Solution Approach 1:
The patent segments the verification process into microtransactions at the transactional level, breaking down large designs with deep loops into smaller, manageable verification units. This segmentation allows the verification tool to handle each microtransaction independently, reducing the overall computational burden and verification time while maintaining completeness through systematic coverage of all segmented portions.
Solution Approach 2:
The patent introduces a new dimension of verification by operating at the transactional level rather than traditional gate or module levels. This dimensional shift enables handling of deep loop designs by transforming the verification problem into a series of transactional equivalences that can be resolved more efficiently, effectively adding a temporal dimension to the verification process.
2Measurement precision
If conventional formal verification methods are used on designs with deep loops, then verification accuracy is maintained, but computational complexity and memory requirements become excessively high
Solution Approach 1:
By segmenting the verification into microtransactions, the patent reduces computational complexity at each step. Each segmented transaction can be verified with simpler computational operations, avoiding the exponential complexity that would arise from verifying the entire deep loop design as a single unit, while maintaining overall verification accuracy through cumulative validation.
Solution Approach 2:
The patent applies partial verification actions at the transactional level, verifying only the necessary portions of the design at each step rather than attempting complete verification of the entire design simultaneously. This partial action approach reduces computational complexity while achieving sufficient verification accuracy for practical purposes.
3Reliability
If conventional formal verification methods are used on designs with deep loops, then thorough verification is achieved, but memory usage exceeds available hardware resources
Solution Approach 1:
The segmentation of verification into microtransactions directly addresses memory constraints by dividing large verification tasks into smaller units that fit within available memory resources. Each segmented transaction requires only a fraction of the memory that would be needed for complete design verification, enabling thorough verification of deep loop designs within practical hardware limits.
Data Source
AI summary
Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions. In certain example embodiments, the disclosed technology involves the formal verification of a register-transfer-level (“RTL”) circuit description produced from a high level synthesis tool (e.g., a C++ or SystemC synthesis tool) relative to the original high level code from which the RTL description was synthesized (e.g., the original C++ or SystemC description) using sub-functional-call-level transactions.