Formal Verification Mutation Coverage via Constraint Segmentation
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Solution Overview
Problem
The high cost and complexity of fixing design errors in semiconductor design phase increase significantly after transitioning to tooling and fabrication, due to cascading effects, making it crucial to identify and rectify errors during the design phase through efficient verification methods.
Innovation Solution
A computer-implemented method for formal verification that generates faults in a cone of influence of an assertion, models the original design with constraints, and initiates verification while ignoring all electronic design constraints, allowing for the activation, deletion, and simulation of faults to create a fault list and identify deadends, thereby reducing the number of constraints required for verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If formal verification is performed with all constraints applied, then verification accuracy is improved, but processing time increases significantly
Solution Approach 1:
The patent segments the constraint set into essential constraints (those required for mathematical certainty of design conformance) and non-essential constraints. The formal verification process applies only essential constraints during verification, while non-essential constraints are temporarily added only when needed for mutation coverage analysis, thereby reducing processing time while maintaining verification accuracy.
Solution Approach 2:
The constraint application is made dynamic rather than static. The system dynamically adjusts which constraints are applied during different phases of verification: essential constraints are always applied, while non-essential constraints are selectively added only when mutation coverage requires them, allowing the verification process to adapt its constraint set based on current needs.
2Reliability
If all constraints are applied during formal verification, then design conformance is ensured, but the number of verification conditions increases
Solution Approach 1:
The patent extracts and identifies which constraints are essential for ensuring design conformance versus which are non-essential. By taking out only the essential constraints for the formal verification process, the system reduces the number of verification conditions while maintaining reliability. Non-essential constraints are separated and applied only when specifically needed for mutation coverage.
3Measurement precision
If mutation coverage is performed without guided constraint management, then test suite effectiveness can be measured, but verification complexity increases
Solution Approach 1:
The system implements feedback mechanisms that monitor verification results and mutation coverage progress. Based on this feedback, the system automatically adjusts which constraints to apply, identifying patterns that indicate when non-essential constraints can be temporarily added for mutation coverage analysis without unnecessarily increasing overall verification complexity.
Data Source
AI summary
The present disclosure relates to a method for formal verification of an integrated circuit design. The method may include providing an electronic design associated with the integrated circuit. The method may further include generating one or more faults in a cone of influence of an assertion and placing a constraint configured to model an original design for the one or more faults. The method may also include initiating formal verification on the electronic design while ignoring all electronic design constraints. The method may further include determining if the assertion is passing, wherein determining includes activating an original design for a subset of faults. If the assertion is passing, the method may include activating a single fault from the subset, determining if the assertion is passing and if the assertion does pass, deleting the single fault from the subset.