Formal Verification Net Splitting for IC Debugging
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Solution Overview
Problem
The high cost and complexity of fixing design errors in semiconductor production increase significantly after the design phase, as small changes can have cascading effects, making it costly to retool entire fabrication lines, and existing formal verification methods are inefficient due to excessive constraint processing.
Innovation Solution
A computer-implemented method for debugging in formal verification of integrated circuits, which involves splitting nets in a cone of influence, placing constraints to rejoin them, identifying unreachable regions, and isolating constraints to reduce the number of constraints required for verification, thereby simplifying the debugging process and reducing processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is performed with all known constraints, then verification completeness is improved, but processing time and complexity increase significantly
Solution Approach 1:
The patent segments the verification process by dividing constraints into two categories: those that must be satisfied and those that are ignored. This segmentation allows the verification tool to focus computational resources on essential constraints while excluding non-essential ones, thereby reducing processing time without compromising the verification of critical design aspects.
Solution Approach 2:
The patent extracts and removes certain constraints from the verification process by identifying a local region of the electronic design and ignoring all constraints associated with that region. This extraction eliminates unnecessary computational overhead while maintaining verification effectiveness for the remaining design portions.
2Reliability
If all constraints are enforced during formal verification, then design correctness is improved, but debugging complexity increases due to unreachable targets
Solution Approach 1:
The patent applies local quality by treating different regions of the electronic design differently. Specifically, it identifies a local region where the target is unreachable and applies a different verification strategy (ignoring constraints) to that local region, while maintaining full constraint enforcement in other regions. This localized approach simplifies debugging by preventing false unreachable target detections in regions where constraints are not applicable.
3Productivity
If design errors are detected after production transitions to tooling and fabrication, then manufacturing progress is improved, but correction cost increases greatly due to retooling requirements
Solution Approach 1:
The patent performs preliminary verification by ignoring certain constraints during formal verification to prevent false detection of unreachable targets. This preliminary action ensures that design errors are accurately identified during the design phase rather than after fabrication, allowing corrections to be made when they are least costly and most easily implemented.
Data Source
AI summary
The present disclosure relates to a method for debugging in the formal verification of an integrated circuit design. The method may include providing, via a computing device, an electronic design associated with the integrated circuit. Embodiments may further include splitting one or more nets in a cone of influence of a target associated with the electronic design. For each split net, embodiments may include placing a constraint that re-joins the net. Embodiments may also include identifying a local region of the electronic design for which the target is unreachable. During formal verification, embodiments may include ignoring all constraints associated with the local region of the electronic design.