Formal Verification via Software Interaction Instruction Sequences
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Solution Overview
Problem
Existing formal verification tools struggle to account for the effects of software interactions on hardware designs, leading to potential undetected problems in hardware designs due to the complexity of software and the requirement for synthesizable software models.
Innovation Solution
The proposed solution involves executing generated instruction sequences captured from software interactions as part of formal verification, allowing for the direct capture and analysis of software effects on hardware designs without requiring synthesizable software models. This is achieved by obtaining software interactions from virtual platforms, emulation, or simulation runs and converting this information into a format usable for formal verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software interactions are directly integrated into formal verification, then verification reliability is improved, but device complexity increases due to the need to handle software models
Solution Approach 1:
The patent extracts software interaction effects from the complex software models and represents them as simplified instruction sequences. This allows the formal verification tool to capture software behavior without needing to fully model the complex software, thereby improving verification reliability while reducing the complexity burden on the verification system.
Solution Approach 2:
The patent introduces an intermediary layer that converts software interactions into a standardized instruction sequence format. This intermediary representation serves as a bridge between the complex software and the formal verification tool, enabling reliable verification without directly handling software complexity.
2Measurement precision
If synthesizable software models are required for formal verification, then verification precision is improved, but ease of manufacture deteriorates due to additional requirements
Solution Approach 1:
The patent extracts only the necessary software interaction effects and represents them as instruction sequences, eliminating the need for complete synthesizable software models. This maintains verification precision by capturing essential software behavior while significantly improving ease of manufacture by removing the synthesizable model requirement.
Solution Approach 2:
The patent uses disposable, non-synthesizable software interaction captures that are converted into verification-friendly instruction sequences. These temporary representations are not meant to be permanent or synthesizable but serve their purpose in verification and can be discarded, eliminating the need for expensive and complex synthesizable model creation.
3Reliability
If software effects are captured through emulation or simulation, then verification reliability is improved, but loss of time increases due to additional verification steps
Solution Approach 1:
The patent performs preliminary capture of software interactions during emulation or simulation runs, converting them into instruction sequences before the formal verification process. This preliminary action captures the software effects in advance, allowing the formal verification to proceed more efficiently without requiring time-consuming iterative processes, thus improving reliability while minimizing time loss.
Data Source
AI summary
Generated instruction sequences captured from software interactions may be executed as part of formal verification of a design under test. Software-instructed commands to be performed to configure a design under test formatted according to an interface implemented by the design under test can be obtained. A sequence to perform the software-instructed commands may be generated to configure the design under test in a hardware design and verification language. The sequence may then be executed to perform the software-instructed commands to configure the design under test and then perform formal verification on the configured design under test.