Forward Counter Architecture With Threshold DMA Offload
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The implementation of counters in ASICs is resource-intensive, leading to significant die area usage, high CPU bandwidth consumption, and inefficient polling mechanisms, which result in increased costs and reduced performance due to the need for frequent updates and checks of counter values.
Innovation Solution
A novel counter architecture that includes local counter storage elements with ALU engines for processing updates, a counter DMA update storage for consolidating and forwarding data, and an external memory interface for maintaining counters in DDR, optimizing die area usage and reducing CPU access instances by using a forwarding counter system with FIFOs and DMA updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full counters are implemented in ASIC, then counting accuracy is improved, but die area usage increases significantly
Solution Approach 1:
The counter is divided into two segments: a small local counter in the ASIC that counts events locally, and a larger counter in CPU memory that stores the accumulated total. The local counter segments the counting function to avoid implementing the full counter in the ASIC, thereby reducing die area while maintaining counting accuracy through periodic updates to the CPU memory counter.
Solution Approach 2:
A counter update mechanism acts as an intermediary between the local ASIC counter and the CPU memory counter. This intermediary transfers the accumulated count from the local counter to the CPU memory counter periodically, enabling accurate long-term counting without requiring the full counter capacity to exist simultaneously in the ASIC.
2Measurement precision
If software polls counters frequently to update upper layer software, then counting accuracy is improved, but CPU bandwidth consumption increases
Solution Approach 1:
Instead of continuous polling, the system uses periodic updates where the local counter accumulates events and transfers its value to the CPU memory counter at predetermined intervals. This periodic action reduces CPU bandwidth consumption compared to frequent polling, while still maintaining accurate counting by ensuring updates occur regularly enough to capture all events.
3Area of stationary object
If smaller counters are used in ASIC with software polling, then die area usage is reduced, but CPU bandwidth consumption increases
Solution Approach 1:
The local counter in the ASIC performs self-service by autonomously counting events and managing its own value accumulation. It automatically transfers its accumulated value to the CPU memory counter when updated, reducing the need for continuous CPU intervention and bandwidth consumption while maintaining accurate counting.
4Measurement precision
If frequent counter updates are performed, then counting accuracy is improved, but system performance decreases
Solution Approach 1:
The system uses periodic updates at predetermined intervals rather than frequent continuous updates. This approach maintains counting accuracy by ensuring the local counter value is transferred to CPU memory regularly, while improving system performance by reducing the frequency of update operations and minimizing CPU bandwidth consumption.
Data Source
AI summary
A forward counter block may include at least one of a plurality of local counter storage elements for counting events. The forward counter block may also include an update engine, the update engine configured to update an external memory by forwarding a value stored in any of said at lease one of a plurality of local counter storage elements and return a zero value to that local counter storage element, when the value stored in that local counter storage element reaches or surpasses a threshold value.