Fosse Spacer Lithography for Semiconductor Overlay Error Mitigation
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Solution Overview
Problem
Current multiple lithography processes in semiconductor fabrication, such as double-lithography and self-aligned double patterning, face challenges in maintaining accurate separation and alignment of features, leading to potential failures in integrated circuit devices due to overlay errors and interactions between submasks.
Innovation Solution
The method involves forming a fosse feature around initial patterned features on a semiconductor substrate, which acts as a spacer to ensure minimum separation distances between subsequent patterned layers, mitigating overlay errors by preventing unwanted interactions and ensuring proper functioning of integrated circuit devices through the use of multiple lithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithography processes are used to pattern smaller features, then manufacturing precision is improved, but overlay errors and alignment issues occur between submasks
Solution Approach 1:
A spacer layer is introduced as an intermediary element between the substrate and the target pattern. The spacer is formed around mandrel structures and defines precise separation distances for subsequent patterning steps, acting as a mediator that ensures accurate feature spacing while accommodating overlay variations in multiple lithography processes
Solution Approach 2:
The spacer and mandrel structures are formed in advance before the actual target pattern is created. This preliminary structuring establishes a framework that guides subsequent lithography steps, ensuring that features are separated by the correct distances even when alignment varies between exposure steps
2Productivity
If feature size is decreased to increase device density, then productivity is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The spacer structures are self-aligned to the mandrel features, automatically defining the correct separation distance without requiring additional alignment steps. This self-service mechanism ensures consistent feature spacing even as overall feature sizes decrease to increase device density
Solution Approach 2:
The spacer thickness and mandrel dimensions are carefully controlled to define the separation distance parameter. By adjusting these geometric parameters, precise feature spacing is achieved regardless of the absolute feature size, enabling high device density while maintaining manufacturing precision
3Area of stationary object
If closer spacing between features is used to increase density, then area is reduced, but unwanted interactions between features occur
Solution Approach 1:
The spacer acts as a physical intermediary that enforces minimum separation distances between features. This mediator structure prevents unwanted electromagnetic or mechanical interactions between closely spaced features while still allowing high density through optimized spacing
Solution Approach 2:
The spacer provides localized separation control at critical interfaces between features. By applying separation only where needed at the spacer-feature interfaces, the design achieves close spacing for high density while preventing harmful interactions through locally enforced quality constraints
Data Source
AI summary
The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.