FOTA Processing Unit for MCU Firmware Updates
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Solution Overview
Problem
Existing methods for updating firmware in computing systems during concurrent operation often result in noticeable latency or low performance due to inefficiencies in managing memory and bus access.
Innovation Solution
The proposed solution involves a system-on-chip (SoC) architecture with a dedicated FOTA processing unit that employs wait states and adaptive polling timers to manage memory operations and bus access, allowing for efficient firmware updates without interrupting system operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If firmware updates are performed during concurrent system operation, then system downtime is reduced, but latency and performance degradation occur
Solution Approach 1:
The patent divides the firmware update process into distinct phases: a first mode where the memory controller operates at full speed for normal system operations, and a second mode where the memory controller is configured with extended timing parameters for firmware updates. The system segments time into update periods and normal operation periods, allowing the memory controller to switch between these modes based on current tasks.
Solution Approach 2:
The memory controller dynamically switches between two operational modes: a first mode with standard timing for high-performance operations and a second mode with extended timing for firmware updates. This dynamic reconfiguration allows the system to optimize performance for the current task, reducing latency during normal operations while enabling concurrent firmware updates during designated update windows.
2Adaptability or versatility
If memory controller settings are changed for firmware writing, then update capability is improved, but read operations performance deteriorates
Solution Approach 1:
The memory controller is configured to dynamically switch between a first set of timing parameters optimized for read operations and a second set of timing parameters optimized for write operations. The controller responds to control signals that indicate whether a read or write operation is required, adjusting its timing characteristics accordingly to maintain optimal performance for the current operation type.
Solution Approach 2:
The system performs firmware updates during predetermined time windows or idle periods when read operations are minimal or scheduled. By anticipating update needs and preparing memory controller settings in advance, the system can switch to update mode with minimal impact on ongoing read operations, thus maintaining read performance while enabling firmware updates.
3Productivity
If bus access is granted to FOTA logic, then firmware update efficiency is improved, but CPU operations experience latency
Solution Approach 1:
The patent introduces a mode register as an intermediary control mechanism between the CPU and the memory controller. The CPU sets specific bits in this mode register to indicate when firmware updates should proceed, allowing the FOTA logic to autonomously control the memory controller during update operations. This intermediary enables efficient firmware updates while minimizing CPU involvement and reducing operational latency.
Solution Approach 2:
The FOTA logic is designed to autonomously manage firmware update operations by directly controlling the memory controller when triggered by CPU-initiated mode register settings. Once the CPU indicates an update should proceed by setting appropriate bits, the FOTA logic independently handles the entire update process including memory controller configuration and data writing, reducing CPU latency while maintaining update efficiency.
Data Source
AI summary
Systems and methods for updating firmware may include using wait states to reduce or eliminate polling by an executing firmware component. An example includes dedicated firmware update hardware logic components, including a firmware update processing unit that executes firmware update code. The firmware update code may be paused between request of a hardware event and completion of a hardware event and under control of one or more of the hardware logic components. Once a hardware event has been completed, a hardware logic component may determine completion and, in response, restart execution of the firmware update code.