FOUP Stocker Interface Buffering for Faster Wafer Throughput

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Solution Overview

Problem

Semiconductor manufacturing processes face throughput bottlenecks due to slow FOUP carrier speeds and insufficient in-process FOUP slots, leading to increased queuing times and contamination risks during wafer merging, which complicates logistics and reduces carrier efficiency.

Innovation Solution

Integration of a FOUP stocker with a high-throughput process tool, featuring adjustable slots that serve as real-time buffers, allowing direct wafer transfers via conveyor belts or robotic arms, and enabling multiple tools to share stockers, optimizing space and resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If FOUP carriers are used to transport wafers between tools, then wafers can be securely held and transported, but the carrier speeds are slow leading to increased throughput time

Engineering Contradiction:
Improvewafer security during transportVSAvoidthroughput speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces an interface module as an intermediary component between the FOUP stocker and the process tool. This interface module includes a transfer module that can directly receive FOUPs from the stocker and transfer them to the process tool without requiring slow carrier transport, thereby improving throughput speed while maintaining wafer security through the controlled interface environment

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system is segmented into distinct functional modules: the FOUP stocker, the interface module with transfer module, and the process tool. This segmentation allows the interface module to handle high-speed transfers independently while the stocker maintains secure storage, resolving the contradiction between secure transport and fast throughput

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If more FOUP slots are provided for in-process wafers, then more wafers can be held simultaneously, but the device complexity and space requirements increase

Engineering Contradiction:
Improvenumber of wafers in processVSAvoidstocker configuration complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The interface module serves multiple functions: it acts as a buffer between the stocker and process tool, provides additional FOUP slot capacity, enables direct transfers, and supports wafer merging operations. This multi-functionality allows the system to handle more wafers simultaneously without proportionally increasing device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The interface module combines the functions of additional FOUP storage slots with the transfer mechanism in a single integrated component. This merging allows the system to increase wafer capacity while avoiding the complexity of separate storage and transfer systems

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If wafers are merged during transport or handling, then carrier efficiency can be improved, but contamination risks increase during the merging process

Engineering Contradiction:
Improvecarrier efficiencyVSAvoidcontamination risk
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The interface module acts as a controlled intermediary environment where wafer merging can occur safely. The module provides a clean, controlled space between the stocker and process tool, allowing wafers to be merged without exposing them to contamination risks that would occur during open handling or transport

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The interface module prepares wafers for processing by performing preliminary merging and staging operations in a controlled environment before they enter the process tool. This preliminary action ensures carrier efficiency is improved while contamination is prevented through the controlled interface environment

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20260005053A1Semiconductor structure and manufacturing method thereof
Publication Date: 2026.01.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260005053A1 patent drawing
  • US20260005053A1 patent drawing
  • US20260005053A1 patent drawing

AI summary

A method includes retrieving a first front opening unified pod (FOUP) from a FOUP stocker utilizing an interface module equipped with a transfer module; transporting the retrieved first FOUP via the transfer module across a first path within the interface module to align the first FOUP with an available first load port of a process tool; loading the first FOUP on the first load port; delivering wafers from the first FOUP to the process tool via the first load port to initiate a wafer processing operation using the wafers.