FOUP Transport System Idle Priority Re-allocation

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Solution Overview

Problem

In semiconductor manufacturing, there is a need for efficient transportation and allocation of Front Opening Unified Pods (FOUPs) between processing machines and storage areas, particularly when the carrier storage apparatus is idle, to prioritize wafers based on their processing stages and storage duration, ensuring optimal utilization and reducing delays.

Innovation Solution

An object carrier transport system comprising a handling unit, control unit, and processing unit that moves carriers between storage sections based on relative priorities, updating these priorities regularly to optimize storage and retrieval operations, allowing for efficient re-allocation of carriers when the apparatus is idle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If carriers are arranged in storage sections based on priority levels, then transportation efficiency and processing capacity utilization are improved, but the complexity of the storage management system increases due to priority tracking and re-allocation operations

Engineering Contradiction:
Improvetransportation efficiencyVSAvoidstorage management system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system performs preliminary arrangement of carriers in storage sections based on their priority levels during idle periods. By proactively organizing carriers before they are needed, the system ensures that high-priority carriers are already positioned for quick retrieval when processing demands arise, thus improving transportation efficiency without adding complexity during active operations

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The storage management system automatically monitors carrier priorities and performs re-allocation operations without external intervention. The control unit continuously tracks carrier status and autonomously executes movements to maintain optimal arrangements, reducing the need for manual management while improving productivity

Inventive Principle:
Principle #25Self-service

2Measurement precision

If the system continuously monitors and updates carrier priorities, then carrier allocation accuracy is improved, but the computational load and system response time increase

Engineering Contradiction:
Improvecarrier allocation accuracyVSAvoidcomputational load
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The system updates carrier priorities and re-arranges storage contents during idle periods rather than continuously during active operations. This periodic action maintains accurate carrier allocation by refreshing priority information when the system is not under time pressure, ensuring precision while minimizing computational load during critical processing phases

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system dynamically adjusts its monitoring and update frequency based on operational status. During idle periods, comprehensive priority updates are performed to maintain accuracy, while during active processing, the system reduces update frequency to lower computational load, adapting its behavior to current system demands

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9618921B2Object carrier transport system and method of transporting object carriers
Publication Date: 2017.04.11 MICRON TECHNOLOGY INC
  • US9618921B2 patent drawing
  • US9618921B2 patent drawing
  • US9618921B2 patent drawing

AI summary

A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines.