Four-Gate Non-Volatile Memory Synapses for Energy-Efficient Neural Networks
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Solution Overview
Problem
Current artificial neural networks face challenges in high-performance information processing due to inadequate hardware technology, specifically high cost and mediocre energy efficiency, which is not comparable to biological networks that perform low-precision analog computation.
Innovation Solution
A neural network device utilizing a combination of CMOS technology and non-volatile memory arrays, where memory cells with floating gates are configured to store weight values, allowing for precise tuning and efficient generation of outputs, enabling continuous programming and individual control of synapses without affecting other memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital supercomputers or specialized graphics processing unit clusters are used to achieve high connectivity between neurons, then computational parallelism is improved, but cost and energy efficiency deteriorate
Solution Approach 1:
The patent replaces digital computing systems with analog circuit implementations. Specifically, it uses analog multipliers and adders constructed from transistors and resistors to perform neural network computations, substituting the mechanical/digital system with an analog electrical system that naturally performs multiplication and addition through circuit operations, thereby improving energy efficiency while maintaining computational parallelism
Solution Approach 2:
The patent combines multiple computational functions into unified circuit structures. The analog multiplier circuits and adder circuits are integrated in a way that performs both multiplication and addition operations simultaneously within the same hardware structure, reducing the number of separate components and improving overall system efficiency
2Use of energy by moving object
If CMOS analog circuits are used for artificial neural networks, then energy efficiency is improved, but device size increases making synapses too bulky
Solution Approach 1:
The patent segments the analog computation functions into distinct modular circuit blocks: separate multiplier circuits with specific transistor configurations and separate adder circuits with resistor networks. This segmentation allows for optimized sizing of each functional unit while maintaining overall energy efficiency, preventing the synapse from becoming excessively large
Solution Approach 2:
The patent optimizes the electrical parameters of the CMOS circuits, including transistor dimensions, resistance values, and operating voltages, to achieve the desired balance between energy efficiency and device size. By carefully selecting and tuning these parameters, the synapse circuits maintain low power consumption while occupying minimal area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the energy efficiency and precision of neural network operations, allowing for fine-tuning of synapse weights and reducing the complexity of separate multiplication and addition logic circuits, thereby improving the overall performance and efficiency of neural networks.
Implementation Method 1
Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate
Implementation Method 2
a first gate disposed over and insulated from a second portion of the channel region, a second gate disposed over and insulated from the floating gate
Data Source
AI summary
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region, and second and third gates over the floating gate and over the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the third gates in one of the memory cell rows, fourth lines each electrically connect the source regions in one of the memory cell rows, and fifth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first, second or third lines, and provide a first plurality of outputs as electrical currents on the fifth lines.