Four-Phase Half-Rate Phase Detector for Low-Latency CDR
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Solution Overview
Problem
Existing phase detectors, such as the Alexander phase detector, require additional logic circuits for oversampling, leading to increased circuit area, power consumption, and latency, which affects the stability of Phase-Locked Loop (PLL) and Clock-Data Recovery (CDR) circuits.
Innovation Solution
A phase detector design that compares data phases using four-phase half-rate clocks with a 90° phase difference, employing multiple sampling circuits and comparators to reduce the logic circuit scale, thereby synchronizing signals with two-phase clocks and processing data in parallel, thus minimizing circuit area, delay time, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional logic circuits are used for oversampling in phase detectors, then phase comparison accuracy is improved, but circuit area increases
Solution Approach 1:
The phase detector is divided into multiple independent sampling circuits, each handling a specific phase comparison task. This segmentation allows parallel processing of phase differences at multiple sampling points, improving accuracy without requiring a single large complex circuit, thus reducing overall circuit area while maintaining precision.
Solution Approach 2:
The patent transitions from single-phase to multi-phase sampling by introducing four-phase half-rate clocks with 90° phase differences. This dimensional expansion in the phase domain enables comprehensive phase comparison across multiple dimensions, achieving higher accuracy through spatial-temporal distribution of sampling operations rather than increasing circuit complexity in a single dimension.
2Measurement precision
If additional logic circuits are used for oversampling in phase detectors, then phase comparison accuracy is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic four-phase half-rate clock signals to perform oversampling at regular intervals. This periodic sampling approach distributes the computational load over time, allowing the circuit to achieve high accuracy through multiple periodic measurements rather than requiring continuously active complex logic circuits, thereby reducing overall power consumption while maintaining precision.
Solution Approach 2:
By segmenting the phase comparison function into multiple simple sampling circuits that operate periodically, the patent reduces the power consumption of individual circuit elements. Each sampling circuit processes only a portion of the phase comparison task, and their results are combined, achieving high accuracy with lower total power consumption compared to a single large continuously-operating circuit.
3Measurement precision
If additional logic circuits are used for oversampling in phase detectors, then phase comparison accuracy is improved, but latency increases
Solution Approach 1:
The phase comparison task is segmented into multiple parallel sampling operations that can be executed simultaneously or in rapid succession. This segmentation eliminates the need for sequential processing through complex logic circuits, reducing the time required to complete phase comparison while maintaining accuracy through multiple sampling points.
Solution Approach 2:
By introducing multiple phase dimensions (four-phase clocks), the patent enables parallel phase comparison operations across different phase references. This dimensional expansion allows the system to gather comprehensive phase information simultaneously rather than sequentially, reducing latency while achieving high measurement accuracy through multi-dimensional sampling.
4Area of stationary object
If logic circuit scale is reduced in phase detectors, then circuit area decreases, but phase comparison capability may be compromised
Solution Approach 1:
The patent segments the phase comparison function into multiple simple sampling circuits, each with minimal logic. This segmentation reduces the complexity and area of individual circuits while collectively maintaining comprehensive phase comparison capability through the combination of multiple simple units, each contributing to the overall measurement accuracy.
Solution Approach 2:
The patent compensates for reduced individual circuit complexity by operating in multiple phase dimensions simultaneously. The four-phase half-rate clock system provides redundant sampling perspectives, ensuring that even simple sampling circuits can achieve accurate phase comparison when their results are integrated across the four phase dimensions, thus maintaining capability with reduced area.
Data Source
AI summary
A phase detector that compares the phases of data and four-phase first to fourth clocks having a half rate of the data and being 90° out of phase with one another. Exemplary embodiments of the phase detector include first to fourth sampling circuits that sample the data by the four-phase first to fourth clocks; a first comparator that compares sampling data obtained by sampling according to the adjacent two-phase first and second clocks using the first and second sampling circuits, respectively, and when the sampling data is different, outputs a first up signal; and a second comparator that compares sampling data obtained by sampling according to the adjacent two-phase fourth and first clocks using the fourth and first sampling circuits, respectively, and when the sampling data is different, outputs a first down signal.