Four-Phase Clock Buffer Topology for Stable 25% Duty Cycle
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Solution Overview
Problem
Existing clock buffers for four-phase, 25% duty cycle clocks are susceptible to errors in duty cycle due to variations in process, supply voltage, and temperature, which can lead to significant deviations in duty cycle, especially in multi-stage scenarios.
Innovation Solution
A four-phase clock buffer design utilizing a common-source ring topology with PMOSTs and NMOSTs, which can output a 4-phase output clock with approximately 75% duty cycle, and can also be adapted to produce a 25% duty cycle output clock by swapping transistor configurations and power supply nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an inverter is used to embody a clock buffer, then the output clock has a larger swing and sharper state transition, but the duty cycle deviates due to differences in PMOS and NMOS pull-up and pull-down strengths
Solution Approach 1:
The clock buffer is divided into four separate inverting clock buffers, each processing one phase of the four-phase input clock. This segmentation allows independent optimization of each buffer while maintaining overall duty cycle accuracy through the specific topology design.
Solution Approach 2:
The patent employs an asymmetric topology where PMOS and NMOS transistors are configured differently within each inverting clock buffer. Specifically, the pull-up and pull-down networks are designed with unequal strengths to compensate for the inherent differences in PMOS and NMOS characteristics, thereby achieving accurate 25% or 75% duty cycles despite process, voltage, and temperature variations.
2Stability of the object's composition
If a cascade of two inverting clock buffers is used to maintain 25% duty cycle, then the duty cycle is preserved, but error accumulates in multi-stage scenarios
Solution Approach 1:
The patent incorporates feedback mechanisms through the specific interconnection of PMOS and NMOS transistors within each inverting clock buffer stage. The topology ensures that each stage independently regenerates the clock signal with the correct duty cycle, preventing error accumulation across multiple stages by effectively resetting the duty cycle at each stage rather than propagating errors.
Solution Approach 2:
The patent changes the operating parameters of the transistors by configuring PMOS and NMOS with specific strength ratios that are optimized for duty cycle regeneration. This parameter optimization ensures that each stage produces the correct output duty cycle regardless of input variations, thereby preventing error accumulation in cascaded multi-stage configurations.
3Ease of operation
If PMOS and NMOS are designed to have equal pull-up and pull-down strength in nominal case, then symmetry is achieved, but duty cycle still deviates under process, supply voltage, and temperature variation
Solution Approach 1:
The patent applies local quality by creating different transistor strength configurations within specific regions of the circuit. Instead of uniform symmetry throughout, each inverting clock buffer has locally optimized PMOS and NMOS strength ratios tailored to compensate for process, voltage, and temperature variations, achieving robust duty cycle performance through localized asymmetry.
Solution Approach 2:
The patent employs preliminary anti-action by pre-configuring the PMOS and NMOS transistor strengths to anticipate and counteract the effects of process, voltage, and temperature variations. The asymmetric design is deliberately chosen to pre-compensate for expected deviations, thereby maintaining duty cycle accuracy under varying operating conditions rather than relying on nominal symmetry.
Data Source
AI summary
A two-stage 4-phase clock buffer having a cascade of a first stage and a second stage, wherein: the first stage includes four p-channel oxide semiconductor transistors (PMOSTs) configured in a common-source ring topology to dispatch a first 4-phase clock, and four n-channel oxide semiconductor transistors (NMOSTs) configured in a common-source topology to control the first 4-phase clock in response to a second 4-phase clock; and, the second stage includes four NMOS transistors configured in a common-source ring topology to dispatch a third 4-phase clock, and four PMOS transistors configured in a common-source topology to control the third 4-phase clock in response to the first 4-phase clock.