Four-Phase Clock Delay Calibration for Equidistant Memory Signals
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Solution Overview
Problem
Current technologies face challenges in testing the duty cycle accuracy of high-speed clock signals and generating equidistant parallel clock signals, which are crucial for improving memory data access rate and stability.
Innovation Solution
A clock generation circuit that includes a four-phase clock generation circuit, signal delay circuit, signal loading circuit, and test circuit to generate and test equidistant clock signals by adjusting signal delays based on duty cycle comparisons, ensuring accurate duty cycle alignment and equidistant signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-speed clock signals are used to improve data processing speed, then productivity increases, but measurement precision of duty cycle deteriorates
Solution Approach 1:
The patent applies preliminary action by generating test clock signals at a lower frequency before the high-speed operation. The duty cycle is tested and adjusted at this lower frequency where measurement is easier and more accurate. Once the duty cycle is calibrated at low frequency, the same circuit configuration is used for high-speed operation, thereby ensuring accurate duty cycle without directly measuring at high speed.
2Loss of time
If duty cycle testing is performed directly on high-speed clock signals, then measurement speed increases, but measurement precision deteriorates
Solution Approach 1:
The patent uses an intermediary approach by introducing a frequency conversion mechanism. Instead of directly testing the high-speed clock signal, the system generates a lower-frequency test signal that serves as an intermediary for duty cycle measurement. This intermediary signal allows accurate measurement while maintaining the benefit of fast testing through automated comparison and adjustment.
3Manufacturing precision
If signal delay adjustment is made to achieve equidistant four-phase signals, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent implements feedback by continuously monitoring the duty cycle of clock signals and automatically adjusting the delay of signal paths based on the test results. The test circuit generates comparison signals that feed back to the delay adjustment mechanism, enabling self-correction of signal equidistance without requiring complex manual calibration circuits. This feedback loop simplifies the overall device structure while maintaining high precision.
Data Source
AI summary
A clock generation circuit, equidistant four-phase signal generation method and memory are provided. The circuit includes: a four-phase clock generation circuit for receiving an internal clock signal and complementary clock signal of a memory to which the clock generation circuit belongs, configured to generate a first, second, third and fourth clock signals with the same cycle; a signal delay circuit configured to perform signal delay on the first clock signal, second clock signal, third clock signal and fourth clock signal respectively based on the delay command, herein the delays of the first clock signal, second clock signal, third clock signal and fourth clock signal are different; a signal loading circuit configured to generate a first indication signal and second indication signal; and a test circuit configured to perform a duty cycle test based on the first indication signal and second indication signal to acquire equidistant parallel clock signals.