Four-Phase Clock Generator Without Duty Converter Overhead
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Solution Overview
Problem
Existing four-phase clock generators with 25% duty cycle require power-consuming duty converters to achieve the desired duty cycle, making them inefficient in terms of power usage.
Innovation Solution
A four-phase 25% duty cycle clock generator is designed using a divide-by-two circuit that directly outputs interim clocks with 25% duty cycle, eliminating the need for a duty converter and enhancing power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a duty converter is used to convert the duty cycle of interim clocks to 25%, then the desired duty cycle is achieved, but power consumption increases
Solution Approach 1:
The patent extracts and eliminates the duty converter component from the clock generation system. By redesigning the divide-by-two circuit to directly generate 25% duty cycle interim clocks, the power-consuming duty converter is removed entirely, resolving the contradiction between achieving precise duty cycle and minimizing power consumption.
Solution Approach 2:
The divide-by-two circuit is designed to perform multiple functions: it divides the input clock frequency by two and simultaneously generates four interim clocks with 25% duty cycle. This multi-functionality eliminates the need for separate duty cycle conversion, reducing overall power consumption while maintaining precision.
2Manufacturing precision
If a duty converter is included to achieve 25% duty cycle, then the clock generation is complete, but the device complexity increases
Solution Approach 1:
The duty converter is extracted and removed from the circuit. The divide-by-two circuit is redesigned to directly produce 25% duty cycle outputs, simplifying the overall device architecture while maintaining the required duty cycle accuracy.
Solution Approach 2:
The frequency division function and duty cycle generation function are merged into a single divide-by-two circuit. This integration eliminates the need for separate duty converter circuits, reducing device complexity while achieving the desired 25% duty cycle accuracy.
3Device complexity
If traditional clock generation methods are used, then the circuit is simpler, but the frequency output is limited
Solution Approach 1:
The clock generation is segmented into four separate interim clocks with 25% duty cycle, each generated by the divide-by-two circuit. This segmentation allows for higher frequency operation while maintaining circuit simplicity, as each phase can be independently optimized and the overall structure remains relatively simple.
Data Source
AI summary
A four-stage gated ring oscillator having four gated amplifiers configured in a ring topology and comprising a first pair of gated amplifiers, controlled by a first phase of an two-phase input clock, interleaved with a second pair gated amplifiers, controlled by a second phase of the two-phase input clock; and two cross-coupling latches configured to provide cross-coupling between the first pair of gated amplifiers and the second pair of gated amplifiers.