Four-Phase Clock Generator Layout for Stable Low-Power Signal Timing
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Solution Overview
Problem
In semiconductor devices like LPDDR5 DRAM, the long paths of read and write clock signals generated from a common clock signal lead to increased current consumption and phase shifts, affecting the efficiency of parallel to serial and serial to parallel conversion operations.
Innovation Solution
A clock signal generation circuit that produces radially propagating divided clock signals, ensuring matched propagation paths and minimizing phase shifts by using buffer circuits and clock drivers arranged symmetrically around a central division circuit, thus stabilizing the phases of read and write clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If read and write clock signals are generated from a common clock signal, then clock signal synchronization is achieved, but the clock signal paths become long leading to increased current consumption and phase shifts
Solution Approach 1:
The patent divides the clock signal generation into multiple independent divided clock signal generation circuits, each generating clock signals for specific functions. This segmentation allows each circuit to use shorter, optimized signal paths while maintaining overall system synchronization, thereby reducing current consumption while preserving phase stability.
Solution Approach 2:
The patent introduces divided clock signals as intermediary signals between the common clock signal and the final read/write clock signals. These intermediary signals are distributed through shorter paths to different functional blocks, reducing the overall path length and current consumption while maintaining synchronization through the common source.
2Stability of the object's composition
If read and write clock signals are generated from a common clock signal, then clock signal synchronization is achieved, but the clock signal paths become long leading to phase shifts
Solution Approach 1:
The patent segments the clock distribution into multiple divided clock signal generation circuits positioned at different locations in the semiconductor device. Each circuit generates clock signals locally for its designated functions, shortening the physical path length while maintaining phase stability through synchronized generation from a common clock source.
Solution Approach 2:
The patent distributes divided clock signal generation circuits across different spatial dimensions and locations within the semiconductor device rather than using a single centralized clock distribution path. This multi-dimensional distribution shortens the maximum signal path length from any clock source to any destination, reducing phase shifts while maintaining synchronization.
3Length of moving object
If divided clock signal generation circuits are distributed at different locations, then clock signal path length is reduced, but circuit complexity increases
Solution Approach 1:
The patent designs each divided clock signal generation circuit to perform multiple functions: generating clock signals for both read and write operations, providing synchronization references, and distributing signals to multiple destinations. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in overall circuit complexity while achieving shorter signal paths.
Solution Approach 2:
The patent varies the configuration parameters of the divided clock signal generation circuits based on their specific locations and functional requirements, such as adjusting the number of buffer circuits or the specific phase divisions. This parameter optimization allows each circuit to be efficiently sized for its role, preventing unnecessary complexity while achieving the goal of shortened signal paths.
Data Source
AI summary
Disclosed herein is an apparatus that includes a clock generator configured to generate first, second, third, and fourth clock signals different in phase from one another, and first, second, third, and fourth clock drivers each configured to drive the first, second, third, and fourth clock signals, respectively. The first and second clock drivers are arranged symmetrically with respect to a first line extending in a first direction. The first and third clock drivers a arranged symmetrically with respect to a second line extending in a second direction. The first and fourth clock drivers are arranged symmetrically with respect to a point crossing the first and second lines.