Four-Phase Clock Generator Layout for Low-Shift DRAM Timing
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Solution Overview
Problem
In semiconductor devices like LPDDR5 DRAM, the long paths of read and write clock signals can lead to significant current consumption and phase shifts, especially when generated from a command address clock, causing inefficiencies in data conversion operations.
Innovation Solution
A semiconductor device design that includes a clock signal generation circuit with a division circuit and buffer circuits to generate four-phase divided clock signals, which are then used to synchronize read and write clock signals, ensuring balanced propagation paths and minimizing phase shifts, thereby optimizing data conversion operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read clock signals and write clock signals are generated from a command address clock signal, then the clock signals can be synchronized with the command address, but the paths of the clock signals become long, leading to large current consumption and phase shifts
Solution Approach 1:
The clock signal generation is segmented into multiple independent sources: a command address clock signal for command/address operations, and separate read/write clock signals for data operations. This segmentation allows each clock path to be optimized independently, shortening the critical paths for read/write clock signals while maintaining synchronization through the shared command address clock source.
2Reliability
If read clock signals and write clock signals are generated from a command address clock signal, then the clock signals can be synchronized with the command address, but the paths of the clock signals become long, causing phase shifts
Solution Approach 1:
The clock signal generation is segmented into multiple independent sources: a command address clock signal for command/address operations, and separate read/write clock signals for data operations. This segmentation allows each clock path to be optimized independently, shortening the critical paths for read/write clock signals while maintaining synchronization through the shared command address clock source.
Solution Approach 2:
The command address clock signal serves as an intermediary reference that indirectly synchronizes the read and write clock signals without requiring them to traverse long paths from a single centralized clock source. This intermediary approach maintains phase coherence while allowing optimized local clock distribution.
3Use of energy by moving object
If four-phase divided clock signals are generated using a division circuit and buffer circuits, then current consumption is reduced and phase shifts are minimized, but the device complexity increases
Solution Approach 1:
The clock signal generation is segmented into multiple independent sources: a command address clock signal for command/address operations, and separate read/write clock signals for data operations. This segmentation allows each clock path to be optimized independently, shortening the critical paths for read/write clock signals while maintaining synchronization through the shared command address clock source.
Solution Approach 2:
The patent generates four-phase divided clock signals (CK0-CK3) with 90-degree phase differences, providing more clock phases than the minimum required for basic read/write operations. This excessive action enables optimized clock distribution and phase alignment without requiring long signal paths, reducing current consumption and phase shifts despite the increased circuit complexity.
Data Source
AI summary
Disclosed herein is an apparatus that includes a clock generator configured to generate first, second, third, and fourth clock signals different in phase from one another, and first, second, third, and fourth clock drivers each configured to drive the first, second, third, and fourth clock signals, respectively. The first and second clock drivers are arranged symmetrically with respect to a first line extending in a first direction. The first and third clock drivers are arranged symmetrically with respect to a second line extending in a second direction. The first and fourth clock drivers are arranged symmetrically with respect to a point crossing the first and second lines.