Four-Phase Shift Register for Stable Short Clock Transitions
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Solution Overview
Problem
In shift registers for monolithic gate drivers, a short clock fall-rise period can lead to display failures due to charge shortages, but setting it shorter to prevent these issues can cause abnormal operations, and existing solutions increase cost and circuit area.
Innovation Solution
A shift register design with four-phase clock signals, where odd and even-order stages receive clock signals with specific phase shifts and on-duty cycles, incorporating output-control switching elements and node charge/discharge units to manage node potentials effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock fall-rise period is shortened to improve charging efficiency, then charge time is reduced, but abnormal operations and display failures occur due to insufficient charge
Solution Approach 1:
The patent applies preliminary action by charging the first node in advance using the pre-stage bistable circuit's output before the main charging operation. This preliminary charge ensures that when the clock fall-rise period is shortened, the node already has sufficient charge储备, preventing display failures while enabling faster operation.
Solution Approach 2:
The patent introduces a new dimension by adding the first node and first-node charge unit to the existing bistable circuit structure. This additional charging path from the pre-stage provides an extra dimension for charge management, allowing the circuit to maintain reliability with shorter clock periods.
2Reliability
If additional circuit elements are added to prevent abnormal operations, then reliability is improved, but circuit area and complexity increase
Solution Approach 1:
The patent applies universality by designing the pre-stage bistable circuit to serve dual functions: it generates the scanning signal for its own stage and simultaneously charges the first node of the current stage. This multi-functionality reduces the need for separate dedicated charging circuits, maintaining reliability without excessive complexity.
Solution Approach 2:
The circuit implements self-service by having each bistable circuit stage automatically charge the first node of the next stage through its output connection. The pre-stage circuit serves the current stage without requiring external control, reducing the need for additional control circuitry while ensuring reliable operation.
3Ease of manufacture
If the circuit configuration is simplified to reduce area and cost, then manufacturing efficiency is improved, but the ability to manage node potentials and prevent abnormal operations is reduced
Solution Approach 1:
The patent merges the charging function into the existing bistable circuit structure by connecting the pre-stage output to the current stage's first node. This consolidation eliminates the need for separate charging circuits while maintaining proper node potential control, achieving both manufacturing efficiency and reliability.
Data Source
AI summary
An object is shortening a clock fall-rise period while suppressing an increase in a circuit area, an increase in current consumption, and a cost increase, without generating an abnormal operation, in a shift register within a monolithic gate driver.In a shift register (410) that operates based on four-phase clock signals, including two-phase clock signals (GCK1, GCK3) that are provided to odd-order stages and two-phase clock signals (GCK2, GCK4) that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock (CKA) appears as a potential of a scanning signal (GOUT), when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.