Four-Slot Asynchronous Communication Mechanism for Data Coherence

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Solution Overview

Problem

Existing four-slot asynchronous communication mechanisms for data transfer between a client and a host system suffer from reduced throughput and increased latency due to significant communication overhead, particularly when used over high-latency buses like PCI or PCI-Express, and can result in data incoherence if the host's reading rate differs from the client's writing rate.

Innovation Solution

A system and method utilizing a four-slot data structure with counter values and 'reading' and 'latest' information bits to ensure data coherence, where the client increments a counter before each write operation and updates 'latest' information, allowing the host to determine the most recently written data without additional DMA operations, thereby reducing the need for extra communication overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a four-slot asynchronous communication mechanism is used to ensure data coherence, then data coherence is improved, but communication overhead increases and throughput decreases

Engineering Contradiction:
Improvedata coherenceVSAvoidthroughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The data transfer process is segmented into distinct phases: the client writes data to a slot and increments a counter, then the host reads the counter value to determine which slot contains the most recent data. This segmentation eliminates the need for additional DMA operations to signal data availability, thereby reducing overhead while maintaining coherence.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The counter value embedded in each slot serves as a self-identifying marker that enables the host to autonomously determine which slot contains the most recent data without requiring additional communication or synchronization operations. This self-service mechanism reduces the communication overhead while ensuring data coherence.

Inventive Principle:
Principle #25Self-service

2Reliability

If additional DMA operations are performed to ensure data coherence, then data coherence is improved, but latency increases

Engineering Contradiction:
Improvedata coherenceVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The client increments the counter value as part of the data write operation itself, preparing the slot with all necessary information (data and counter) before the host needs to read it. This preliminary action eliminates the need for subsequent DMA operations to signal data availability, thereby reducing latency while ensuring coherence.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If locking mechanisms are used to prevent data incoherence, then data coherence is improved, but timing interference increases

Engineering Contradiction:
Improvedata coherenceVSAvoidtiming interference
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the synchronization function from traditional locking mechanisms and implements it through the counter value embedded in each slot. Instead of using locks to prevent data incoherence, the system uses the counter to identify the most recent data, thereby eliminating timing interference while maintaining coherence.

Inventive Principle:
Principle #2Taking out (Extraction)

4Adaptability or versatility

If the host's reading rate differs from the client's writing rate, then operational flexibility is improved, but data incoherence becomes possible

Engineering Contradiction:
Improveoperational flexibilityVSAvoiddata coherence
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The counter value provides continuous feedback to the host about which slot contains the most recent data. This feedback mechanism allows the host to adapt to varying write rates and maintain data coherence regardless of the difference between reading and writing rates, thereby improving both operational flexibility and reliability.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8135879B2Four-slot asynchronous communication mechanism with increased throughput
Publication Date: 2012.03.13 NATIONAL INSTRUMENTS CORP
  • US8135879B2 patent drawing
  • US8135879B2 patent drawing
  • US8135879B2 patent drawing

AI summary

System and method for a four-slot asynchronous communication mechanism with increased throughput. The system may include a host system and a client device. The host may comprise a data structure with four (two pairs of) slots and first information indicating a status of read operations from the data structure by the host. The client may read the first information from the host. The client may read second information from a local memory. The second information may indicate a status of write operations to the data structure by the client. The client may determine a slot of the data structure to be written. The slot may be determined based on the first information and the second information and may be the slot which has not been written to more recently of the pair of slots which has not been read from most recently. The client may increment a value of a counter. The value of the counter may be useable to indicate which slot has been written to most recently. The client may write data to the determined slot in the data structure on the host. The data may include the value of the counter. The client may update the second information in the local memory to indicate that the determined slot has been written to most recently.