Four-Terminal Transistor Gate Segmentation for Leakage Control
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Solution Overview
Problem
Conventional CMOS technology faces challenges as device feature sizes decrease, leading to difficulties in manufacturing and maintaining integrity of thin gate insulating layers, which affects control over transistor channels and increases current leakage.
Innovation Solution
The use of four-terminal junction field effect transistors (4T JFETs) with separate control of the channel between source and drain through both a front gate and a back gate, allowing for various operational modes and reduced device count in logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate insulating layer thickness is decreased to provide adequate control over the channel in scaled CMOS transistors, then control over the channel is improved, but manufacturing difficulty increases and integrity is compromised
Solution Approach 1:
The transistor gate control is segmented into two independent gates (front gate and back gate), allowing each gate to independently control the channel. This segmentation enables adequate channel control without requiring excessively thin gate insulating layers, as the combined control of both gates provides the necessary control authority while maintaining manufacturable thicknesses for individual gate insulating layers.
2Manufacturing precision
If gate insulating layer thickness is decreased to provide adequate control over the channel, then control over the channel is improved, but device reliability deteriorates due to lost integrity
Solution Approach 1:
By dividing the gate control into two separate gates with their own insulating layers, the system achieves the required control authority without compromising the integrity of individual insulating layers. Each gate insulating layer can be manufactured at a reliable thickness, and the combined effect of both gates provides adequate channel control.
Solution Approach 2:
The back gate structure provides localized control over the channel region, allowing independent optimization of the front gate and back gate insulating layers. This local quality approach enables each insulating layer to be designed with appropriate thickness for both control authority and reliability, rather than requiring one extremely thin layer to provide all control.
3Productivity
If conventional CMOS technology is used to reduce device feature sizes, then integration density is improved, but current leakage increases
Solution Approach 1:
The back gate voltage can be dynamically adjusted to optimize the off-state characteristics of the transistor. By applying appropriate back gate bias, the depletion region can be extended to suppress leakage currents, while maintaining the ability to achieve full enhancement mode operation when both gates are actively driven. This dynamic control allows the device to maintain low leakage across scaled feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient control of channel impedance, reduces device count in integrated circuits, and improves current leakage characteristics compared to conventional CMOS technology, while maintaining operational reliability.
Implementation Method 1
In response to a voltage applied at control gate 1910, a depletion region can be altered to change the conductivity between source 1930 and drain 1920
Data Source
AI summary
Circuits using four terminal transistors are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal transistors operating in a linear or nonlinear mode.