Four-Transistor FeFET Memory Circuit Layout Area Reduction
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Solution Overview
Problem
Current volatile memory technologies, such as SRAM, require six transistors to store each memory bit and face challenges in reducing write and read disturb, leading to increased complexity and power consumption.
Innovation Solution
A four-transistor memory circuit with a single inverter is proposed, utilizing ferroelectric field effect transistors (FeFETs) or negative capacitance FETs (NCFETs) to store two states with different applied voltages, reducing the layout area and improving write and read access times by minimizing voltage variations during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional SRAM is used to store each memory bit, then the memory can maintain stored information as long as power is connected, but the layout area is larger and requires six transistors per bit
Solution Approach 1:
The patent combines multiple functions into a single inverter structure that can store one bit of information using only four transistors. The inverter's feedback mechanism integrates the storage function that traditionally required six separate transistors in SRAM, reducing both the transistor count and layout area while maintaining volatile memory functionality.
Solution Approach 2:
The patent changes the operational parameters by using non-volatile memory characteristics (hysteresis behavior, remnant polarization) within a volatile memory architecture. This allows the four-transistor inverter to achieve stable state retention without requiring the traditional six-transistor SRAM structure, thereby reducing area and complexity.
2Reliability
If traditional SRAM is used, then volatile memory functionality is achieved, but write and read disturb issues increase operational complexity and power consumption
Solution Approach 1:
The patent exploits the hysteresis parameter and remnant polarization properties of non-volatile memory materials to create a volatile memory structure that is inherently more resistant to write and read disturb. The inverter's feedback mechanism, combined with these material properties, creates stable state retention that reduces the need for frequent refresh operations, thereby lowering power consumption while improving reliability.
Solution Approach 2:
The patent uses a simplified four-transistor inverter structure that can be manufactured with fewer process steps and less material than traditional six-transistor SRAM. This reduction in manufacturing complexity translates to lower production costs and enables the deployment of more memory cells per chip area, effectively reducing the power consumption per bit of stored information.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The four-transistor memory circuit achieves write and read disturb-free operations with reduced power consumption and faster access times, outperforming traditional SRAM in terms of layout efficiency and operational stability.
Implementation Method 1
utilizing ferroelectric field effect transistors (FeFETs) or negative capacitance FETs (NCFETs) to store two states with different applied voltages
Implementation Method 2
utilizing ferroelectric field effect transistors (FeFETs) or negative capacitance FETs (NCFETs) to store two states with different applied voltages
Data Source
AI summary
A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.