Four-Wire Embedded Clock Signaling to Cut SerDes Complexity
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Solution Overview
Problem
High-speed digital data communications in processors face challenges with parallel communication techniques due to increased complexity, area consumption, and power usage, while serializer/deserializer (SerDes) technology is complex and adds design effort, die area consumption, and potential failure points, especially when used for on-die communications.
Innovation Solution
A digital receiver system using four wires with three signaling levels (-1, 0, +1) embeds the clock signal within the data stream, allowing for simultaneous transmission of two data bits and a clock signal, minimizing external interaction and eliminating the need for separate clock lines, thereby reducing power consumption and design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel data communication technique is used, then data transmission rate can be increased, but power consumption and power supply noise increase due to buffers drawing large dynamic currents
Solution Approach 1:
The patent combines the clock signal transmission with data signal transmission by encoding them together on the same four-wire differential interface. The three-state signaling levels (-1, 0, +1) allow simultaneous representation of clock and data bits, eliminating the need for separate clock lines and reducing power consumption while maintaining high data transmission rates.
Solution Approach 2:
The patent changes the signaling parameter from traditional two-state (0, 1) to three-state (-1, 0, +1) differential signaling. This parameter change enables the interface to encode both clock and data information within the same signal levels, reducing the need for additional buffering and dynamic current draw while preserving high-speed communication capabilities.
2Speed
If SerDes technology is used, then data communication rate can be increased, but device complexity and die area consumption increase
Solution Approach 1:
The patent merges clock signal generation and data signal transmission into a single integrated interface using four differential wires with three-state signaling. This eliminates the need for separate SerDes modules, clock distribution networks, and associated control logic, thereby reducing device complexity while achieving high-speed communication.
Solution Approach 2:
The four-wire differential interface serves multiple functions simultaneously: it transmits both clock and data signals, provides differential signaling for noise immunity, and enables high-speed communication without requiring separate dedicated circuits for each function. This multi-functionality reduces overall system complexity compared to traditional SerDes approaches.
3Stability of the object's composition
If separate clock lines are used for parallel communication, then clock synchronization can be maintained, but electromagnetic interference and power supply noise increase
Solution Approach 1:
The patent merges clock and data signal transmission into the same four-wire differential interface using three-state signaling levels. By encoding clock information within the data transmission signals themselves, the system maintains clock synchronization without requiring separate clock lines, thereby eliminating the electromagnetic interference and power supply noise that would result from additional high-speed clock traces.
Solution Approach 2:
The patent converts what would traditionally be a harmful separation (requiring separate clock lines that generate EMI) into a beneficial integrated approach. By embedding clock synchronization within the data transmission signals, the system eliminates the source of electromagnetic interference while maintaining stable clocking through the differential signaling mechanism itself.
Data Source
AI summary
A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.