N-Point Complex Fourier Transform Structure Reducing Multiplies
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current digital signal processing in radar and radio applications requires efficient matrix-vector multiplication operations, which are often complex and resource-intensive, particularly for large matrices and vectors, leading to high computational costs and power consumption.
Innovation Solution
A logic structure for chip integration that performs matrix-vector multiplication by treating single bits of each matrix row at a time, forming combinations of vector elements as sums and differences, and using precomputed combinations to reduce the number of multiplication operations, allowing for parallel processing and efficient computation of matrix-vector products.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional FFT is used for Fourier analysis, then the number of complex multiply/accumulate operations is reduced to N log2(N), but the computational complexity and power consumption remain high for large N
Solution Approach 1:
The patent segments the matrix-vector multiplication into processing individual bits of matrix rows sequentially. Each bit position is processed independently, forming combinations of vector elements based on bit patterns. This segmentation transforms the conventional N log2(N) complex multiply/accumulate operations into a structure requiring only N real multiplies for N-point DFT, significantly reducing computational complexity and power consumption while maintaining accuracy.
2Productivity
If matrix-vector multiplication is performed using conventional methods, then all operations are completed, but the number of multiplication operations is large and computational cost is high
Solution Approach 1:
The patent applies preliminary action by pre-forming combinations of vector elements based on bit patterns before the actual multiplication. Combinations of vector elements are pre-computed and stored, then selected and summed according to the bit patterns of matrix rows. This eliminates the need for numerous individual multiplication operations, reducing computational resources from O(N²) to O(N) for DFT operations.
3Use of energy by moving object
If the number of multiplication operations is reduced, then power consumption decreases, but the computational approach becomes more complex
Solution Approach 1:
The patent substitutes the conventional mechanical multiplication operation with a combination of addition and pre-computed lookups. Instead of performing numerous multiply/accumulate operations, the system forms combinations of vector elements through addition based on bit patterns, then selects and sums these combinations. This substitution replaces complex multiplication hardware with simpler addition logic and lookup tables, reducing power consumption while managing complexity through systematic organization.
Data Source
AI summary
An integrated circuit chip implementing multiplication of an M×N element matrix with an N-element vector to obtain an M-element product by combining the vector with rows of bits of the same significance selected from the matrix one bit-row at a time to form partial products, exploiting the fact that the same potential combinations are needed for all bit-rows and all matrix rows to precompute all of the combinations once and for all, and combining selected partial products for different bit place-significance with a shift-and-add operation only once for each of the M product elements, thereby effectively using only M multiply-equivalent structures. An N-point Complex Fourier Transform can therefore be claimed which only needs 2N real multiplies and the product of an N×N matrix with another N×N matrix requires only N2 multiplies.